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1. 发明授权

US07406083B2 Method for preserving the order of data packets processed along different processing paths 失效
标题翻译：用于保持沿着不同处理路径处理的数据分组的顺序的方法
公开(公告)号：US07406083B2
公开(公告)日：2008-07-29
申请号：US10645104
申请日：2003-08-21
申请人： Gero Dittmann , Laurent Frelechoux , Andreas Herkersdorf
发明人： Gero Dittmann , Laurent Frelechoux , Andreas Herkersdorf
IPC分类号： H04L12/28 , H04L12/56 , H04L12/54 , H04J3/02
CPC分类号： H04L47/34 , H04L47/24 , H04L47/50
摘要： Described is a method and system for processing data packets of a data stream in a communication system. The data packets are processed depending on a feature of the header of a data packet in a faster path or in a slower path. To avoid a disorder by the different processing paths, the fast processed data packets are stored in a memory. The stored fast processed data packets are output after all slowly processed data packets which before the processing were in order before the fast data packets have been put to the output. In this way, the processed data packets are in the same order as prior to the processing.
摘要翻译：描述了一种用于处理通信系统中的数据流的数据分组的方法和系统。数据分组根据数据分组头部的特征在更快的路径或较慢的路径中被处理。为了避免不同处理路径的混乱，快速处理的数据包被存储在存储器中。存储的快速处理的数据包在所有缓慢处理的数据包之前被输出，在处理之前，快速数据包被放入输出之前。以这种方式，处理的数据分组的处理顺序与处理之前相同。

2. 发明授权

US07307951B2 Timeout determination method and apparatus 有权
标题翻译：超时确定方法和装置
公开(公告)号：US07307951B2
公开(公告)日：2007-12-11
申请号：US10417258
申请日：2003-04-17
申请人： Gero Dittmann , Andreas Herkersdorf
发明人： Gero Dittmann , Andreas Herkersdorf
IPC分类号： H04J3/16 , H04L12/66
CPC分类号： H04L69/28 , H04L43/026
摘要： A method (and apparatus) for determining, in a system including an m-bit time counter, whether an event-occurrence time lies after a predetermined timeout-value, includes reading out of a time-stamp memory a stored time-stamp value, determining the time-difference between the time-stamp value and the event-occurrence time, and determining whether the time-difference is larger than the predetermined timeout-value. The event-occurrence time is represented by a subset of the bits of the m-bit time counter, the subset being determined by a plurality of parameters including any two of a lower bit-position, an upper bit-position, and a subset width. The lower bit-position is dependent on the predetermined timeout-value.
摘要翻译：一种用于在包括m位时间计数器的系统中确定事件发生时间是否位于预定超时值之后的方法（和装置）包括：读出时间戳存储器存储的时间戳值，确定所述时间戳值与所述事件发生时间之间的时差，以及确定所述时差是否大于所述预定超时值。事件发生时间由m位时间计数器的位的子集表示，该子集由多个参数确定，包括较低位位置，高位位置和子集宽度中的任何两个。较低位位置取决于预定的超时值。

3. 发明申请

US20050152354A1 Method and systems for ordered dynamic distribution of packet flows over network processing means 有权
标题翻译：通过网络处理手段对数据包流进行有序动态分配的方法和系统
公开(公告)号：US20050152354A1
公开(公告)日：2005-07-14
申请号：US10506101
申请日：2003-02-27
申请人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
发明人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
IPC分类号： H04L12/801 , H04L12/803 , H04L12/851 , H04L29/08 , H04L12/28
CPC分类号： H04L67/1008 , H04L47/10 , H04L47/125 , H04L47/2441 , H04L47/2483 , H04L47/34 , H04L67/1002
摘要： A method and systems for dynamically distributing packet flows over multiple network processing means and recombining packet flows after processing while keeping packet order even for traffic wherein an individual flow exceeds the performance capabilities of a single network processing means is disclosed. After incoming packets have been analyzed to identify the flow the packets are parts of, the sequenced load balancer of the invention dynamically distributes packets to the connected independent network processors. A balance history is created per flow and updated each time a packet of the flow is received and/or transmitted. Each balance history memorizes, in time order, the identifier of network processor having handled packets of the flow and the associated number of processed packets. Processed packets are then transmitted back to a high-speed link or memorized to be transmitted back to the high-speed link later, depending upon the current status of the balance history.
摘要翻译：一种用于在多个网络处理装置上动态地分发分组流的方法和系统，并且在处理之后重新组合分组流，同时保持分组顺序，即使对于单个流超过单个网络处理装置的性能的流量也是如此。在分析了输入数据包以识别数据包是流量的一部分后，本发明的顺序负载平衡器动态地将分组分发到连接的独立网络处理器。每个流创建一个平衡历史，并在每次接收和/或发送流的数据包时进行更新。每个平衡历史按时间顺序记录已处理流的分组的处理器的数据包的标识符和相关联的处理数据包的数量。处理的数据包然后被发送回到高速链路或存储，以根据当前的平衡历史状态稍后传送回高速链路。

4. 发明授权

US07359318B2 Method and systems for ordered dynamic distribution of packet flows over network processing means 有权
标题翻译：通过网络处理手段对数据包流进行有序动态分配的方法和系统
公开(公告)号：US07359318B2
公开(公告)日：2008-04-15
申请号：US10506101
申请日：2003-02-27
申请人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
发明人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
IPC分类号： H04J3/14 , H04J1/16
CPC分类号： H04L67/1008 , H04L47/10 , H04L47/125 , H04L47/2441 , H04L47/2483 , H04L47/34 , H04L67/1002
摘要： A method and systems for dynamically distributing packet flows over multiple network processing means and recombining packet flows after processing while keeping packet order even for traffic wherein an individual flow exceeds the performance capabilities of a single network processing means is disclosed. After incoming packets have been analyzed to identify the flow the packets are parts of, the sequenced load balancer of the invention dynamically distributes packets to the connected independent network processors. A balance history is created per flow and updated each time a packet of the flow is received and/or transmitted. Each balance history memorizes, in time order, the identifier of network processor having handled packets of the flow and the associated number of processed packets. Processed packets are then transmitted back to a high-speed link or memorized to be transmitted back to the high-speed link later, depending upon the current status of the balance history.
摘要翻译：一种用于在多个网络处理装置上动态地分发分组流的方法和系统，并且在处理之后重新组合分组流，同时保持分组顺序，即使对于单个流超过单个网络处理装置的性能的流量也是如此。在分析了输入数据包以识别数据包是流量的一部分后，本发明的顺序负载平衡器动态地将分组分发到连接的独立网络处理器。每个流创建一个平衡历史，并在每次接收和/或发送流的数据包时进行更新。每个平衡历史按时间顺序记录已处理流的分组的处理器的数据包的标识符和相关联的处理数据包的数量。处理的数据包然后被发送回到高速链路或存储，以根据当前的平衡历史状态稍后传送回高速链路。

5. 发明授权

US06768716B1 Load balancing system, apparatus and method 有权
标题翻译：负载平衡系统，装置和方法
公开(公告)号：US06768716B1
公开(公告)日：2004-07-27
申请号：US09551049
申请日：2000-04-18
申请人： François G. Abel , Peter Buchmann , Antonius Engbersen , Andreas Herkersdorf , Ronald P. Luijten , David J. Webb
发明人： François G. Abel , Peter Buchmann , Antonius Engbersen , Andreas Herkersdorf , Ronald P. Luijten , David J. Webb
IPC分类号： H04J304
CPC分类号： H04L29/06 , G06F9/50 , H04L69/12
摘要： A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.
摘要翻译：一种用于将从高速通信线路发出的输入数据分组序列分发到多个处理装置的实时负载平衡系统，每个处理装置以低于高速通信线路的容量的容量运行; 根据本发明的系统包括：解析器，其能够从所述输入分组提取可配置的分类器比特集合，以馈送到压缩装置; 压缩装置能够将长度K的位模式减小为长度L为K的一部分的位图案; 用于延迟输入分组直到发现负载平衡决定的流水线块;以及反向解复用器，用于接收从所述压缩装置输出的端口标识符作为选择器，并将流水线分组引导到适当的输出端口。

6. 发明授权

US07603540B2 Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
标题翻译：使用现场可编程门阵列（FPGA）技术与微处理器进行可重配置，指令级硬件加速
公开(公告)号：US07603540B2
公开(公告)日：2009-10-13
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F9/00 , G06F15/00
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

7. 发明授权

US07584345B2 System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
标题翻译：使用FPGA技术与微处理器进行可重配置，指令级硬件加速的系统
公开(公告)号：US07584345B2
公开(公告)日：2009-09-01
申请号：US10696865
申请日：2003-10-30
申请人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGA in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising thecoprocessor and processor are provided as well.
摘要翻译：一种用于动态编程现场可编程门阵列的方法（协处理器中的FPGA，耦合到处理器的协处理器）包括：由处理器开始执行应用程序;从处理器接收指令到协处理器以执行应用程序的功能 ;确定协处理器中的FPGA没有用该功能的逻辑编程;获取功能的配置位流;以及使用配置位流编程FPGA，以这种方式，FPGA可以“即时”编程，即在应用程序的执行过程中动态执行，由FPGA提供的硬件加速和资源共享优势可以被应用程序更频繁地利用，同时提供了包括微处理器和处理器在内的芯片的逻辑灵活性和空间节省。

8. 发明授权

US07493412B2 Method for processing a data packet 失效
标题翻译：数据包处理方法
公开(公告)号：US07493412B2
公开(公告)日：2009-02-17
申请号：US10658311
申请日：2003-09-09
申请人： Andreas Herkersdorf , Jan Van Lunteren
发明人： Andreas Herkersdorf , Jan Van Lunteren
IPC分类号： H04L12/28 , G06F15/173
CPC分类号： H04L45/00 , H04L45/742 , H04L45/7457
摘要： The invention is directed to methods, apparatus and systems for processing a data packet that has a destination address. In the event that in a routing table cache and in a routing table, there is no entry with a destination address prefix that is a prefix of the destination address, a default-route-prefix is determined in a default-route determination step.
摘要翻译：本发明涉及用于处理具有目的地地址的数据分组的方法，装置和系统。在路由表缓存和路由表中，没有目的地址前缀是目的地址前缀的条目，在默认路由确定步骤中确定默认路由前缀。

9. 发明授权

US6058119A SDH/sonet interface 失效
标题翻译： SDH / sonet接口
公开(公告)号：US6058119A
公开(公告)日：2000-05-02
申请号：US930837
申请日：1997-10-07
申请人： Antonius P. Engbersen , Andreas Herkersdorf , Wolfram Lemppenau , Hans R Schindler
发明人： Antonius P. Engbersen , Andreas Herkersdorf , Wolfram Lemppenau , Hans R Schindler
IPC分类号： H04J3/00 , H04J3/16 , H04L12/70 , H04L25/03 , H04Q3/00 , H04Q11/04
CPC分类号： H04J3/1617 , H04L25/03866 , H04Q11/0478 , H04J2203/0096 , H04L2012/5672 , H04L2012/5673 , Y10S370/907
摘要： A modular approach to the mapping of data in and from a standard SDH/SONET signal is described. A module has interfaces (T0-T8) which allows to connect to it to other of its kind and thereby achieving higher data rates, i.e. access to standard signals of higher levels. By choosing among different interconnection schemes, arrangements comprising a plurality of modules are also able to support concatenated data traffic.
摘要翻译： PCT No.PCT / EP95 / 01426 Sec。 371日期1997年10月7日第 102（e）日期1997年10月7日PCT提交1995年4月15日PCT公布。出版物WO96 / 33563 日期1996年10月24日描述了标准SDH / SONET信号中数据映射的模块化方法。模块具有接口（T0-T8），其允许将其连接到其他类型，从而实现更高的数据速率，即访问更高级别的标准信号。通过选择不同的互连方案，包括多个模块的布置也能够支持级联的数据业务。

10. 发明授权

US5271000A Method and apparatus for testing and evaluation of distributed networks 失效
标题翻译：分布式网络的测试和评估方法和装置
公开(公告)号：US5271000A
公开(公告)日：1993-12-14
申请号：US804133
申请日：1991-12-06
申请人： Antonius J. Engbersen , Marco Heddes , Andreas Herkersdorf , Ronald Luijten , Ernst Rothauser
发明人： Antonius J. Engbersen , Marco Heddes , Andreas Herkersdorf , Ronald Luijten , Ernst Rothauser
IPC分类号： H04L12/26 , H04L12/56 , H04Q11/04 , H04L1/24
CPC分类号： H04L43/50 , H04L12/2697 , H04Q11/0478 , H04L2012/5628
摘要： The dynamic functional behavior of geographically distributed fast packet switching systems, including those which accommodate high-priority circuit switched traffic and low-priority packet switched traffic, are tested in real-time by sending test packets from one or more source nodes through the system to specific destinations that comprise a test packet analyzer. The test packets have the same structure as the data packets, but in their payload portion carry the entire information required to perform the testing. The nature of that test information depends on the characteristics of a set of predefined system errors the verification system is supposed to identify. For detecting errors, the test information would include an input address indicating the source of the test packet, a sequence number defining the order in which the packet should arrive at the destination, time bits relating to the packet length and/or to the expected packet transmission delay, and a cyclic redundancy code which covers the entire contents of the test packet, including its control portion. Each analyzer at a receiving station operates autonomously from the senders and processes all received traffic in real-time; this enables it to recognize all defined system errors, even those occurring with very low probability, at the packet level.

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