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1. 发明授权

US08495542B2 Automated management of verification waivers 失效
标题翻译：自动管理验证豁免
公开(公告)号：US08495542B2
公开(公告)日：2013-07-23
申请号：US13234952
申请日：2011-09-16
申请人： Gero Dittmann
发明人： Gero Dittmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/504
摘要： Automated management of verification waivers is disclosed. In one embodiment a method is provided comprising issuing a request to perform a verification run on a component of an electric circuit design, receiving configuration data specifying a list of waivers extracted from a plurality of waivers applicable to the electric circuit design as a whole where the list of waivers is extracted based on waiver validity period data and is applicable to the component rather than the electric circuit design as a whole. The described method further comprises identifying a potential design defect and generating a verification run result including a set of design defects of the component, the set including the potential design defect if no waiver of the list of waivers is determined to be applicable.
摘要翻译：披露了自动管理验证豁免。在一个实施例中，提供了一种方法，包括发出对电路设计的部件执行验证运行的请求，接收指定从适用于整个电路设计的多个放弃中提取的放弃列表的配置数据，其中，根据豁免有效期数据提取豁免清单，适用于整体而不是电路设计。所描述的方法还包括识别潜在的设计缺陷并产生包括该组件的一组设计缺陷的验证运行结果，该集合包括如果放弃的列表的放弃被确定为可应用的，则该集合包括潜在的设计缺陷。

2. 发明申请

US20050152354A1 Method and systems for ordered dynamic distribution of packet flows over network processing means 有权
标题翻译：通过网络处理手段对数据包流进行有序动态分配的方法和系统
公开(公告)号：US20050152354A1
公开(公告)日：2005-07-14
申请号：US10506101
申请日：2003-02-27
申请人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
发明人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
IPC分类号： H04L12/801 , H04L12/803 , H04L12/851 , H04L29/08 , H04L12/28
CPC分类号： H04L67/1008 , H04L47/10 , H04L47/125 , H04L47/2441 , H04L47/2483 , H04L47/34 , H04L67/1002
摘要： A method and systems for dynamically distributing packet flows over multiple network processing means and recombining packet flows after processing while keeping packet order even for traffic wherein an individual flow exceeds the performance capabilities of a single network processing means is disclosed. After incoming packets have been analyzed to identify the flow the packets are parts of, the sequenced load balancer of the invention dynamically distributes packets to the connected independent network processors. A balance history is created per flow and updated each time a packet of the flow is received and/or transmitted. Each balance history memorizes, in time order, the identifier of network processor having handled packets of the flow and the associated number of processed packets. Processed packets are then transmitted back to a high-speed link or memorized to be transmitted back to the high-speed link later, depending upon the current status of the balance history.
摘要翻译：一种用于在多个网络处理装置上动态地分发分组流的方法和系统，并且在处理之后重新组合分组流，同时保持分组顺序，即使对于单个流超过单个网络处理装置的性能的流量也是如此。在分析了输入数据包以识别数据包是流量的一部分后，本发明的顺序负载平衡器动态地将分组分发到连接的独立网络处理器。每个流创建一个平衡历史，并在每次接收和/或发送流的数据包时进行更新。每个平衡历史按时间顺序记录已处理流的分组的处理器的数据包的标识符和相关联的处理数据包的数量。处理的数据包然后被发送回到高速链路或存储，以根据当前的平衡历史状态稍后传送回高速链路。

3. 发明授权

US07406083B2 Method for preserving the order of data packets processed along different processing paths 失效
标题翻译：用于保持沿着不同处理路径处理的数据分组的顺序的方法
公开(公告)号：US07406083B2
公开(公告)日：2008-07-29
申请号：US10645104
申请日：2003-08-21
申请人： Gero Dittmann , Laurent Frelechoux , Andreas Herkersdorf
发明人： Gero Dittmann , Laurent Frelechoux , Andreas Herkersdorf
IPC分类号： H04L12/28 , H04L12/56 , H04L12/54 , H04J3/02
CPC分类号： H04L47/34 , H04L47/24 , H04L47/50
摘要： Described is a method and system for processing data packets of a data stream in a communication system. The data packets are processed depending on a feature of the header of a data packet in a faster path or in a slower path. To avoid a disorder by the different processing paths, the fast processed data packets are stored in a memory. The stored fast processed data packets are output after all slowly processed data packets which before the processing were in order before the fast data packets have been put to the output. In this way, the processed data packets are in the same order as prior to the processing.
摘要翻译：描述了一种用于处理通信系统中的数据流的数据分组的方法和系统。数据分组根据数据分组头部的特征在更快的路径或较慢的路径中被处理。为了避免不同处理路径的混乱，快速处理的数据包被存储在存储器中。存储的快速处理的数据包在所有缓慢处理的数据包之前被输出，在处理之前，快速数据包被放入输出之前。以这种方式，处理的数据分组的处理顺序与处理之前相同。

4. 发明申请

US20100057404A1 Optimal Performance and Power Management With Two Dependent Actuators 审中-公开
标题翻译：具有两个独立执行器的最佳性能和电源管理
公开(公告)号：US20100057404A1
公开(公告)日：2010-03-04
申请号：US12201877
申请日：2008-08-29
申请人： Gero Dittmann , Alper Buyuktosunoglu , Indira Nair , Reinaldo A. Bergamaschi
发明人： Gero Dittmann , Alper Buyuktosunoglu , Indira Nair , Reinaldo A. Bergamaschi
IPC分类号： G06F19/00 , G05B13/02
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Techniques for processor chip power management and performance optimization are provided. In one aspect, a method for maximizing performance of a processor chip within a given power consumption budget is provided. The method comprises the following steps. A power consumption and performance of the processor chip at all possible voltage level and frequency combinations is predicted. The processor chip is adjusted to the voltage level and frequency combination that provides the highest performance while having a power consumption that does not exceed the power budget. After a time interval t1, the frequency of the processor chip is varied to accommodate for any shift in workload to maintain the highest performance within the power budget. After a time interval t2, the adjust and vary steps are repeated, wherein time interval t2 is greater than time interval t1.
摘要翻译：提供了处理器芯片功率管理和性能优化的技术。在一个方面，提供了一种用于在给定功耗预算内最大化处理器芯片的性能的方法。该方法包括以下步骤。预测在所有可能的电压电平和频率组合下的处理器芯片的功耗和性能。处理器芯片被调整到提供最高性能的电压电平和频率组合，同时具有不超过功率预算的功耗。在时间间隔t1之后，改变处理器芯片的频率以适应任何工作量的变化，以在功率预算内维持最高性能。在时间间隔t2之后，重复调整和改变步骤，其中时间间隔t2大于时间间隔t1。

5. 发明授权

US07307951B2 Timeout determination method and apparatus 有权
标题翻译：超时确定方法和装置
公开(公告)号：US07307951B2
公开(公告)日：2007-12-11
申请号：US10417258
申请日：2003-04-17
申请人： Gero Dittmann , Andreas Herkersdorf
发明人： Gero Dittmann , Andreas Herkersdorf
IPC分类号： H04J3/16 , H04L12/66
CPC分类号： H04L69/28 , H04L43/026
摘要： A method (and apparatus) for determining, in a system including an m-bit time counter, whether an event-occurrence time lies after a predetermined timeout-value, includes reading out of a time-stamp memory a stored time-stamp value, determining the time-difference between the time-stamp value and the event-occurrence time, and determining whether the time-difference is larger than the predetermined timeout-value. The event-occurrence time is represented by a subset of the bits of the m-bit time counter, the subset being determined by a plurality of parameters including any two of a lower bit-position, an upper bit-position, and a subset width. The lower bit-position is dependent on the predetermined timeout-value.
摘要翻译：一种用于在包括m位时间计数器的系统中确定事件发生时间是否位于预定超时值之后的方法（和装置）包括：读出时间戳存储器存储的时间戳值，确定所述时间戳值与所述事件发生时间之间的时差，以及确定所述时差是否大于所述预定超时值。事件发生时间由m位时间计数器的位的子集表示，该子集由多个参数确定，包括较低位位置，高位位置和子集宽度中的任何两个。较低位位置取决于预定的超时值。

6. 发明申请

US20120072878A1 AUTOMATED MANAGEMENT OF VERIFICATION WAIVERS 失效
标题翻译：自动化验证管理
公开(公告)号：US20120072878A1
公开(公告)日：2012-03-22
申请号：US13234952
申请日：2011-09-16
申请人： Gero Dittmann
发明人： Gero Dittmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/504
摘要： Automated management of verification waivers is disclosed. In one embodiment a method is provided comprising issuing a request to perform a verification run on a component of an electric circuit design, receiving configuration data specifying a list of waivers extracted from a plurality of waivers applicable to the electric circuit design as a whole where the list of waivers is extracted based on waiver validity period data and is applicable to the component rather than the electric circuit design as a whole. The described method further comprises identifying a potential design defect and generating a verification run result including a set of design defects of the component, the set including the potential design defect if no waiver of the list of waivers is determined to be applicable.
摘要翻译：披露了自动管理验证豁免。在一个实施例中，提供了一种方法，包括发出对电路设计的部件执行验证运行的请求，接收指定从适用于整个电路设计的多个放弃中提取的放弃列表的配置数据，其中，根据豁免有效期数据提取豁免清单，适用于整体而不是电路设计。所描述的方法还包括识别潜在的设计缺陷并产生包括该组件的一组设计缺陷的验证运行结果，该集合包括如果放弃的列表的放弃被确定为可应用的，则该集合包括潜在的设计缺陷。

7. 发明授权

US08001405B2 Self-tuning power management techniques 有权
标题翻译：自整定电源管理技术
公开(公告)号：US08001405B2
公开(公告)日：2011-08-16
申请号：US12201821
申请日：2008-08-29
申请人： Gero Dittmann , Reinaldo A. Bergamaschi , Indira Nair , Alper Buyuktosunoglu
发明人： Gero Dittmann , Reinaldo A. Bergamaschi , Indira Nair , Alper Buyuktosunoglu
IPC分类号： G06F1/26 , G06F1/00 , G06F11/00 , G01R21/00
CPC分类号： G06F1/3203
摘要： Power management techniques include a method for power management of a processor chip which comprises the following steps. An initial operating level is set for the processor chip. After a predetermined time interval, slack is calculated. If the slack is greater than zero, the initial operating level is increased to a next higher level, otherwise the initial operating level is maintained. After the predetermined time interval, the slack is re-calculated and further includes accumulated slack. If the re-calculated slack is greater than zero, the operating level is increased to the next higher level if the processor chip is being operated at the initial operating level, otherwise the operating level is returned to the initial operating level if the processor chip is being operated at the next higher operating level. The steps to re-calculate the slack and either increase the operating level to the next higher level or return the operating level to the initial operating level are repeated.
摘要翻译：电源管理技术包括用于处理器芯片的电源管理的方法，其包括以下步骤。为处理器芯片设置初始操作级别。在预定的时间间隔之后，计算松弛。如果松弛度大于零，则初始操作级别增加到下一级，否则保持初始操作级别。在预定的时间间隔之后，重新计算松弛，并进一步包括累积的松弛。如果重新计算的松弛大于零，则如果处理器芯片在初始操作电平下操作，则操作电平增加到下一个较高电平，否则如果处理器芯片为在下一个更高的运行水平运行。重新计算松弛的步骤，并将操作级别提高到下一级，或将操作级别恢复到初始操作级别。

8. 发明申请

US20100058084A1 Self-Tuning Power Management Techniques 有权
标题翻译：自调节电源管理技术
公开(公告)号：US20100058084A1
公开(公告)日：2010-03-04
申请号：US12201821
申请日：2008-08-29
申请人： Gero Dittmann , Reinaldo A. Bergamaschi , Indira Nair , Alper Buyuktosunoglu
发明人： Gero Dittmann , Reinaldo A. Bergamaschi , Indira Nair , Alper Buyuktosunoglu
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： Power management techniques include a method for power management of a processor chip which comprises the following steps. An initial operating level is set for the processor chip. After a predetermined time interval, slack is calculated. If the slack is greater than zero, the initial operating level is increased to a next higher level, otherwise the initial operating level is maintained. After the predetermined time interval, the slack is re-calculated and further includes accumulated slack. If the re-calculated slack is greater than zero, the operating level is increased to the next higher level if the processor chip is being operated at the initial operating level, otherwise the operating level is returned to the initial operating level if the processor chip is being operated at the next higher operating level. The steps to re-calculate the slack and either increase the operating level to the next higher level or return the operating level to the initial operating level are repeated.
摘要翻译：电源管理技术包括用于处理器芯片的电源管理的方法，其包括以下步骤。为处理器芯片设置初始操作级别。在预定的时间间隔之后，计算松弛。如果松弛度大于零，则初始操作级别增加到下一级，否则保持初始操作级别。在预定的时间间隔之后，重新计算松弛，并进一步包括累积的松弛。如果重新计算的松弛大于零，则如果处理器芯片在初始操作电平下操作，则操作电平增加到下一个较高电平，否则如果处理器芯片为在下一个更高的运行水平运行。重新计算松弛的步骤，并将操作级别提高到下一级，或将操作级别恢复到初始操作级别。

9. 发明授权

US07359318B2 Method and systems for ordered dynamic distribution of packet flows over network processing means 有权
标题翻译：通过网络处理手段对数据包流进行有序动态分配的方法和系统
公开(公告)号：US07359318B2
公开(公告)日：2008-04-15
申请号：US10506101
申请日：2003-02-27
申请人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
发明人： Francois Abel , Alan Benner , Gero Dittmann , Andreas Herkersdorf
IPC分类号： H04J3/14 , H04J1/16
CPC分类号： H04L67/1008 , H04L47/10 , H04L47/125 , H04L47/2441 , H04L47/2483 , H04L47/34 , H04L67/1002
摘要： A method and systems for dynamically distributing packet flows over multiple network processing means and recombining packet flows after processing while keeping packet order even for traffic wherein an individual flow exceeds the performance capabilities of a single network processing means is disclosed. After incoming packets have been analyzed to identify the flow the packets are parts of, the sequenced load balancer of the invention dynamically distributes packets to the connected independent network processors. A balance history is created per flow and updated each time a packet of the flow is received and/or transmitted. Each balance history memorizes, in time order, the identifier of network processor having handled packets of the flow and the associated number of processed packets. Processed packets are then transmitted back to a high-speed link or memorized to be transmitted back to the high-speed link later, depending upon the current status of the balance history.
摘要翻译：一种用于在多个网络处理装置上动态地分发分组流的方法和系统，并且在处理之后重新组合分组流，同时保持分组顺序，即使对于单个流超过单个网络处理装置的性能的流量也是如此。在分析了输入数据包以识别数据包是流量的一部分后，本发明的顺序负载平衡器动态地将分组分发到连接的独立网络处理器。每个流创建一个平衡历史，并在每次接收和/或发送流的数据包时进行更新。每个平衡历史按时间顺序记录已处理流的分组的处理器的数据包的标识符和相关联的处理数据包的数量。处理的数据包然后被发送回到高速链路或存储，以根据当前的平衡历史状态稍后传送回高速链路。

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