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1. 发明授权

US08492844B2 Fully depleted SOI device with buried doped layer 有权
标题翻译：具有掩埋掺杂层的完全耗尽的SOI器件
公开(公告)号：US08492844B2
公开(公告)日：2013-07-23
申请号：US13305206
申请日：2011-11-28
申请人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofmann , Carlos Mazure
发明人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofmann , Carlos Mazure
IPC分类号： H01L27/088 , H01L29/36 , H01L21/8238
CPC分类号： H01L27/10894 , H01L21/84 , H01L27/10876 , H01L27/1207 , H01L29/4236 , H01L29/66621
摘要： The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
摘要翻译：本发明涉及通过提供第一基板来制造半导体器件的方法; 在所述第一衬底的表面区域中提供掺杂层; 在所述掺杂层上提供掩埋氧化物层; 在掩埋氧化物层上提供半导体层以获得绝缘体上半导体（SeOI）晶片; 从所述SeOI晶片的第一区域去除所述掩埋氧化物层和所述半导体层，同时将所述掩埋氧化物层和所述半导体层保持在所述SeOI晶片的第二区域中; 通过在掺杂层中或由掺杂层形成背栅，在第二区域中提供上晶体管; 以及通过在掺杂层中或由掺杂层形成源极和漏极区域来在第一区域中提供下部晶体管。

2. 发明申请

US20120181609A1 FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER 有权
标题翻译：完全覆盖的SOI器件与BEDIED DOPED层
公开(公告)号：US20120181609A1
公开(公告)日：2012-07-19
申请号：US13305206
申请日：2011-11-28
申请人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofman , Carlos Mazure
发明人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofman , Carlos Mazure
IPC分类号： H01L27/088 , H01L29/36 , H01L21/8238
CPC分类号： H01L27/10894 , H01L21/84 , H01L27/10876 , H01L27/1207 , H01L29/4236 , H01L29/66621
摘要： The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
摘要翻译：本发明涉及通过提供第一基板来制造半导体器件的方法; 在所述第一衬底的表面区域中提供掺杂层; 在所述掺杂层上提供掩埋氧化物层; 在掩埋氧化物层上提供半导体层以获得绝缘体上半导体（SeOI）晶片; 从所述SeOI晶片的第一区域去除所述掩埋氧化物层和所述半导体层，同时将所述掩埋氧化物层和所述半导体层保持在所述SeOI晶片的第二区域中; 通过在掺杂层中或由掺杂层形成背栅，在第二区域中提供上晶体管; 以及通过在掺杂层中或由掺杂层形成源极和漏极区域来在第一区域中提供下部晶体管。

3. 发明授权

US09159400B2 Semiconductor memory having staggered sense amplifiers associated with a local column decoder 有权
标题翻译：具有与本地列解码器相关联的交错读出放大器的半导体存储器
公开(公告)号：US09159400B2
公开(公告)日：2015-10-13
申请号：US13422697
申请日：2012-03-16
申请人： Richard Ferrant , Gerhard Enders , Carlos Mazure
发明人： Richard Ferrant , Gerhard Enders , Carlos Mazure
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/4097
摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.
摘要翻译：具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。这导致互连空间与位线平行。此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

4. 发明申请

US20120243360A1 SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED WITH A LOCAL COLUMN DECODER 有权
标题翻译：具有与本地色谱柱解码器相关的STAGGEREN SENSE放大器的半导体存储器
公开(公告)号：US20120243360A1
公开(公告)日：2012-09-27
申请号：US13422697
申请日：2012-03-16
申请人： Richard Ferrant , Gerhard Enders , Carlos Mazure
发明人： Richard Ferrant , Gerhard Enders , Carlos Mazure
IPC分类号： G11C7/06 , G11C8/10
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/4097
摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.
摘要翻译：具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。这导致互连空间与位线平行。此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

5. 发明授权

US09490264B2 Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device 有权
标题翻译：具有通过掩埋绝缘层的半导体区域之间的接触的器件，以及用于制造所述器件的工艺
公开(公告)号：US09490264B2
公开(公告)日：2016-11-08
申请号：US12984466
申请日：2011-01-04
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/12 , H01L21/74 , H01L21/84 , H01L27/108 , H01L29/732 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10802 , H01L27/10873 , H01L29/732 , H01L29/7841 , H01L29/78639
摘要： The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.
摘要翻译：本发明涉及一种在绝缘体上半导体衬底上制造的半导体器件，其包括通过掩埋绝缘层与基底衬底分离的半导体材料的薄层，该器件包括薄层中的第一导电区域，第二导电层区域和通过绝缘层将第一区域连接到第二区域的接触。本发明还涉及制造这种半导体器件的方法。

6. 发明授权

US08654602B2 Pseudo-inverter circuit on SeOI 有权
标题翻译： SeOI上的伪逆变电路
公开(公告)号：US08654602B2
公开(公告)日：2014-02-18
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

7. 发明授权

US08508289B2 Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer 有权
标题翻译： SeOI衬底上的数据通道单元，在绝缘层下面带有一个后控制栅极
公开(公告)号：US08508289B2
公开(公告)日：2013-08-13
申请号：US13013580
申请日：2011-01-25
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G05F1/10 , H01L27/105 , G06F17/50
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/11807 , H01L27/1203
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区，，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。这种电路结构还包括连接背栅极控制区域的后栅极线。本发明还提供了操作和设计这种半导体器件结构的方法。

8. 发明申请

US20110242926A1 PSEUDO-INVERTER CIRCUIT ON SeO1 有权
标题翻译： PSO1上的PSEUDO-INVERTER电路
公开(公告)号：US20110242926A1
公开(公告)日：2011-10-06
申请号：US12793553
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F1/10
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

9. 发明授权

US07919393B2 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate 有权
标题翻译：在基材上包含松弛或假松弛层的成形结构
公开(公告)号：US07919393B2
公开(公告)日：2011-04-05
申请号：US12769299
申请日：2010-04-28
申请人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
发明人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76259 , H01L21/324 , H01L21/76254 , H01L2221/68363
摘要： A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.
摘要翻译：一种用于形成在衬底上包括松弛或假松弛层的结构的方法。该方法包括在施主衬底上生长半导体材料的弹性应力层的步骤; 在应力层上形成粘性材料的玻璃状层; 去除供体衬底的一部分以形成包括玻璃层，应力层和供体衬底材料的表面层的结构; 图案化应力层; 并且在至少玻璃质层的粘度温度的温度下对结构进行热处理，以使应力层松弛以形成结构的松弛或假松弛层。

10. 发明授权

US07736988B2 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate 有权
标题翻译：在基材上包含松弛或假松弛层的成形结构
公开(公告)号：US07736988B2
公开(公告)日：2010-06-15
申请号：US11345495
申请日：2006-02-02
申请人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
发明人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
IPC分类号： H01L21/76 , H01L21/30 , H01L21/46
CPC分类号： H01L21/76259 , H01L21/324 , H01L21/76254 , H01L2221/68363
摘要： A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.
摘要翻译：描述了在衬底上形成松弛或假松弛有用层的方法。该方法包括在施主衬底上生长应变半导体层，通过在某一粘度温度下变得粘稠的材料的玻璃质层将接收器衬底接合到应变半导体层以形成第一结构。该方法还包括从第一结构分离施主衬底以形成包括接受衬底，玻璃体层和应变层的第二结构，然后在足够的温度和时间对第二结构进行热处理以使应变中的应变松弛并且在接收器基板上形成松弛或假松弛的有用层。

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