专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06349383B1 System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution 有权
标题翻译：将相邻的推/堆栈程序指令组合为单个双推/弹出堆栈微程序执行的系统
公开(公告)号：US06349383B1
公开(公告)日：2002-02-19
申请号：US09151006
申请日：1998-09-10
申请人： Gerard M. Col , G. Glenn Henry , Arturo Martin-de-Nicolas
发明人： Gerard M. Col , G. Glenn Henry , Arturo Martin-de-Nicolas
IPC分类号： G06F9312
CPC分类号： G06F9/3017 , G06F9/3004 , G06F9/3816 , G06F9/3824
摘要： An apparatus and method are provided for combining multiple instructions prescribing accesses to a microprocessor stack into a single micro instruction. The apparatus includes a translator and access alignment logic. The translator receives a first stack access instruction and a second stack access instruction from an instruction queue, and decodes them into an associated micro instruction directing the microprocessor to accomplish both accesses prescribed by the stack access instructions during a combined access, wherein the combined access is achieved in a single instruction cycle. The access alignment logic is coupled to the translator and indicates alignment of two data entities within a cache for the combined access. The two stack access instructions are not combined when the access alignment logic indicates that the combination of the data entities is misaligned within the cache.
摘要翻译：提供了一种装置和方法，用于将处理对微处理器堆栈的访问的多个指令组合成单个微指令。该装置包括翻译器和访问对准逻辑。翻译器从指令队列接收第一堆栈访问指令和第二堆栈访问指令，并且将它们解码为指示微处理器在组合访问期间完成堆栈访问指令规定的两个访问的关联微指令，其中组合访问是在单个指令周期内实现。访问对准逻辑耦合到翻译器并且指示用于组合访问的高速缓存内的两个数据实体的对齐。当访问对准逻辑指示数据实体的组合在缓存内未对齐时，两个堆栈访问指令不被组合。

2. 发明授权

US06209082B1 Apparatus and method for optimizing execution of push all/pop all instructions 有权
标题翻译：优化push all / pop all指令执行的装置和方法
公开(公告)号：US06209082B1
公开(公告)日：2001-03-27
申请号：US09193278
申请日：1998-11-17
申请人： Gerard Col , G. Glenn Henry , Arturo Martin-de-Nicolas
发明人： Gerard Col , G. Glenn Henry , Arturo Martin-de-Nicolas
IPC分类号： G06F9312
CPC分类号： G06F9/3005 , G06F9/3017 , G06F9/3816
摘要： An apparatus and method are provided for executing a push all/pop all instruction in a pipeline microprocessor. The apparatus includes an instruction buffer and a translator. The instruction buffer provides the push all/pop all instruction, directing the microprocessor to store/retrieve multiple operands to/from a stack. The translator generates a sequence of micro instructions to store/retrieve the multiple operands. Accesses to a pair of operands which are together aligned are combined into a single access.
摘要翻译：提供了一种用于在流水线微处理器中执行全部/全部推送指令的装置和方法。该装置包括指令缓冲器和转换器。指令缓冲区提供push all / pop all指令，指示微处理器将/多个操作数存储/从堆栈中检索。翻译器生成一系列微指令来存储/检索多个操作数。一起对齐的一对操作数的访问被组合成单个访问。

3. 发明授权

US5889679A Fuse array control for smart function enable 失效
标题翻译：保险丝阵列控制智能功能使能
公开(公告)号：US5889679A
公开(公告)日：1999-03-30
申请号：US892640
申请日：1997-07-15
申请人： G. Glenn Henry , Arturo Martin-de-Nicolas , Daniel G. Miner
发明人： G. Glenn Henry , Arturo Martin-de-Nicolas , Daniel G. Miner
IPC分类号： G06F15/78 , G06F15/00
CPC分类号： G06F15/7867
摘要： An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and logically merges the fuse states with a default configuration for the functional blocks. The result of the merge operation is stored in a feature control register that individually enables/disables the functional blocks. The control unit also receives a write command from an external source that modifies the feature control register, after the device is shipped from the manufacturer. The control unit selectively blocks writes to the feature control register that attempt to enable/disable functional blocks that should not modified.
摘要翻译：提供了一种用于智能配置半导体器件内的功能块的装置和方法。熔丝阵列包含在制造中被吹制的多个保险丝，以使/禁用半导体器件上的功能块。控制单元读取保险丝的状态，并将保险丝状态逻辑合并为功能块的默认配置。合并操作的结果存储在单独启用/禁用功能块的功能控制寄存器中。在设备从制造商出货之后，控制单元还从外部源接收修改特征控制寄存器的写命令。控制单元有选择地阻止对特征控制寄存器的写入，该寄存器尝试启用/禁用不应修改的功能块。

4. 发明授权

US07532722B2 Apparatus and method for performing transparent block cipher cryptographic functions 有权
标题翻译：用于执行透明块密码加密功能的装置和方法
公开(公告)号：US07532722B2
公开(公告)日：2009-05-12
申请号：US10727973
申请日：2003-12-04
申请人： Thomas A. Crispin , G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
IPC分类号： H04L9/00
CPC分类号： G06F9/3001 , G06F9/30007 , G06F9/30043 , G06F9/3017 , G06F9/30178 , G06F9/325 , G06F9/3885 , G06F21/72 , H04L9/0631 , H04L9/0637 , H04L2209/125 , H04L2209/24
摘要： The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and execution logic. The cryptographic instruction is received by a computing device as part of an instruction flow executing on the computing device, wherein the cryptographic instruction prescribes one of the cryptographic operations. The execution logic is operatively coupled to the cryptographic instruction and executes the one of the cryptographic operations. The one of the cryptographic operations includes indicating whether the one of the cryptographic operations has been interrupted by an interrupting event.
摘要翻译：本发明提供一种用于对处理器内的多个输入数据块执行密码操作的装置和方法。在一个实施例中，提供了一种用于执行密码操作的装置。该装置包括密码指令和执行逻辑。密码指令由计算设备接收，作为在计算设备上执行的指令流的一部分，其中密码指令规定了一个密码操作。执行逻辑可操作地耦合到密码指令，并执行加密操作之一。加密操作之一包括指示密码操作中的一个是否已被中断事件中断。

5. 发明授权

US07162612B2 Mechanism in a microprocessor for executing native instructions directly from memory 有权
标题翻译：在微处理器中直接从存储器执行本地指令的机制
公开(公告)号：US07162612B2
公开(公告)日：2007-01-09
申请号：US10761845
申请日：2004-01-21
申请人： G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
发明人： G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
IPC分类号： G06F5/00
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30189
摘要： An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external instruction bus, and translates each of the macro instructions into associated native instructions for execution. If a first form of a first macro instruction is retrieved, the instruction translation logic directs the microprocessor to enable a native bypass mode and indicates such by asserting a first bit within a control register. The bypass logic is coupled to the instruction translation logic. The bypass logic accesses the first bit within the control register to determine if the native bypass mode has been enabled, and detects wrapper macro instructions and, upon detection of the wrapper macro instructions, disables the instruction translation logic, and provides the native instructions for execution by the microprocessor, thereby bypassing the instruction translation logic.
摘要翻译：提供了一种用于直接从存储器执行本机指令的微处理器装置和方法。该装置包括指令转换逻辑和旁路逻辑。指令转换逻辑检索通过外部指令总线提供的宏指令，并且将每个宏指令转换成相关联的本机指令以供执行。如果检索到第一宏指令的第一形式，则指令转换逻辑指示微处理器启用本机旁路模式，并通过断言控制寄存器中的第一位来指示。旁路逻辑耦合到指令转换逻辑。旁路逻辑访问控制寄存器中的第一位以确定本机旁路模式是否已启用，并检测包装宏指令，并且在检测到包装宏指令时，禁用指令转换逻辑，并提供本机指令执行由微处理器绕过指令转换逻辑。

6. 发明授权

US07712105B2 Microprocessor including random number generator supporting operating system-independent multitasking operation 有权
标题翻译：微处理器包括随机数发生器，支持独立于操作系统的多任务操作
公开(公告)号：US07712105B2
公开(公告)日：2010-05-04
申请号：US11428308
申请日：2006-06-30
申请人： G. Glenn Henry , Terry Parks , Arturo Martin-de-Nicolas
发明人： G. Glenn Henry , Terry Parks , Arturo Martin-de-Nicolas
IPC分类号： G06F9/46 , G06F1/02 , G06F9/44
CPC分类号： G06F9/30101 , G06F9/3863 , G06F9/461
摘要： A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The CSR is not saved and restored by the OS. The RNG shadows the CSR with an SSE register that is saved and restored by the OS. A new instruction loads the CSR, and also loads the shadowed SSE register. Whenever the SSE register is restored from memory, the RNG sets a flag indicating that a possible task switch occurred. Whenever the processor executes a new instruction that stores the random data to memory, it checks the flag and copies the control values from the SSE register to the CSR if the flag is true, discards previously generated bytes, and restarts random number generation.
摘要翻译：一个微处理器，包括一个随机数发生器（RNG），可以在没有操作系统（OS）支持的情况下在任务交换机上保存和恢复其自身状态。 RNG包括用于存储影响随机数生成的控制值的控制和状态寄存器（CSR）。 CSR不会由操作系统保存和恢复。 RNG使用由操作系统保存和恢复的SSE寄存器来影响CSR。一个新的指令加载了CSR，并加载了阴影的SSE寄存器。每当从内存中恢复SSE寄存器时，RNG设置一个标志，指示可能的任务切换发生。每当处理器执行将随机数据存储到存储器的新指令时，它检查标志，并将控制值从SSE寄存器复制到CSR，如果标志为真，则丢弃先前生成的字节，并重新启动随机数生成。

7. 发明授权

US07136991B2 Microprocessor including random number generator supporting operating system-independent multitasking operation 有权
公开(公告)号：US07136991B2
公开(公告)日：2006-11-14
申请号：US10300931
申请日：2002-11-20
申请人： G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
发明人： G. Glenn Henry , Arturo Martin-de-Nicolas , Terry Parks
IPC分类号： G06F9/48
CPC分类号： G06F9/30101 , G06F9/3863 , G06F9/461
摘要： A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The CSR is not saved and restored by the OS. The RNG shadows the CSR with an SSE register that is saved and restored by the OS. A new instruction loads the CSR, and also loads the shadowed SSE register. Whenever the SSE register is restored from memory, the RNG sets a flag indicating that a possible task switch occurred. Whenever the processor executes a new instruction that stores the random data to memory, it checks the flag and copies the control values from the SSE register to the CSR if the flag is true, discards previously generated bytes, and restarts random number generation.

8. 发明授权

US09032189B2 Efficient conditional ALU instruction in read-port limited register file microprocessor 有权
标题翻译：读端口限制寄存器文件微处理器中有效的条件ALU指令
公开(公告)号：US09032189B2
公开(公告)日：2015-05-12
申请号：US13333520
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30094 , G06F9/30141 , G06F9/30174
摘要： A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.
摘要翻译：一种微处理器，其执行结构指令，指示其在第一和第二源操作数上执行操作以产生结果，并且仅当其结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令转换器将指令转换为第一和第二微指令。要执行第一个微指令，执行流水线对源操作数执行操作以生成结果。要执行第二个微指令，如果架构条件标志满足条件，则将目标寄存器写入由第一微指令生成的结果，如果结构条件标志不满足条件标志，则将目标寄存器写入目标寄存器的当前值条件。

9. 发明授权

US08924695B2 Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor 有权
标题翻译：条件ALU指令条件满足在读端口限制寄存器文件微处理器中的微指令之间的传播
公开(公告)号：US08924695B2
公开(公告)日：2014-12-30
申请号：US13333631
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30123 , G06F9/30174
摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.
摘要翻译：架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令翻译器将架构指令转换为第一和第二微指令。为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

10. 发明授权

US08880857B2 Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor 有权
标题翻译：条件ALU指令在读端口限制寄存器文件微处理器中的微指令之前进行移位生成的进位标志传播
公开(公告)号：US08880857B2
公开(公告)日：2014-11-04
申请号：US13333572
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30094 , G06F9/30174
摘要： A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags.
摘要翻译：微处理器包括将架构指令转换成第一和第二微指令的硬件指令转换器。为了执行第一微指令，执行流水线对第一源操作数执行移位操作以产生第一结果和进位标志值，并且利用所生成的进位标志值更新非架构进位标志。为了执行第二微指令，它对第一结果和第二操作数执行第二操作，以基于第二结果产生第二结果和新条件标志值。如果架构条件标志满足条件，则使用非架构进位标志值来更新架构进位标志，并用对应的生成的新条件标志值来更新其他架构状态标志中的至少一个; 否则，它使用架构条件标志的当前值更新架构条件标志。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式