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1. 发明授权

US06769052B2 Cache with selective write allocation 有权
标题翻译：具有选择性写入分配的缓存
公开(公告)号：US06769052B2
公开(公告)日：2004-07-27
申请号：US10157555
申请日：2002-05-29
申请人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0804 , Y02D10/13
摘要： A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation lookaside buffer (TLB) (310n) is connected to receive a request virtual address from each respective processor. A set of address regions (pages) is defined within an address space of a back-up memory associated with the cache and write allocation in the cache is defined on a page basis. Each TLB has a set of entries that correspond to pages of address space and each entry provides a write allocate attribute (550) for the associated page of address space. During operation of the system, software programs are executed and memory transactions are performed. A write allocate attribute signal (550) is provided with each write transaction request. In this manner, the attribute signal is responsive to the value of the write allocation attribute bit assigned to an address region that includes the address of the write transaction request. Write allocation in the cache memory is performed generally in accordance with the write allocate attribute signal. However, write allocation policy circuitry (560) is also provided and operates to refine the operation of the write allocation. Thus, the cache memory is responsive to the write policy circuitry such that write allocation is performed in a selective manner in accordance to the attribute signal for a first write policy state and write allocation is always performed in accordance to the attribute signal for a second write policy state.
摘要翻译：提供了数字系统和操作方法，其中多个处理器（590n）连接到共享高速缓存存储器资源（500）。连接翻译后备缓冲器（TLB）（310n）以从每个相应的处理器接收请求虚拟地址。在与高速缓存相关联的备份存储器的地址空间内定义一组地址区（页），并且以页为基础定义高速缓存中的写分配。每个TLB具有对应于地址空间的页面的一组条目，并且每个条目为相关联的地址空间页面提供写入分配属性（550）。在系统操作期间，执行软件程序并执行存储器事务。写入分配属性信号（550）被提供有每个写事务请求。以这种方式，属性信号响应于分配给包括写事务请求地址的地址区的写分配属性位的值。通常根据写入分配属性信号来执行高速缓冲存储器中的写入分配。然而，还提供了写分配策略电路（560）并且操作以改进写分配的操作。因此，高速缓冲存储器响应于写策略电路，使得根据用于第一写策略状态的属性信号以选择的方式执行写分配，并且总是根据用于第二写的属性信号执行写分配政策状态。

2. 发明授权

US07496930B2 Accessing device driver memory in programming language representation 有权
标题翻译：以编程语言表示访问设备驱动程序内存
公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G06F3/14 , G09G5/393
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译：在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用设备驱动。在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。应用数据结构可以存储单维数据结构或多维数据结构。在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。

3. 发明申请

US20050033945A1 Dynamically changing the semantic of an instruction 审中-公开
标题翻译：动态地改变指令的语义
公开(公告)号：US20050033945A1
公开(公告)日：2005-02-10
申请号：US10830917
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
IPC分类号： G06F9/22 , G06F9/318 , G06F9/44 , G06F11/34 , G06F12/00 , G06F9/30
CPC分类号： G06F11/3466 , G06F9/30087 , G06F9/30174 , G06F9/30189 , G06F2201/865 , G06F2201/88
摘要： A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic may comprise the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction's operation (e.g., the inclusion of read or write barrier operations to support a garbage collector).
摘要翻译：一种技术包括接收指令并基于与指令分离的可编程信息来动态地改变指令的语义。语义的变化可以包括包括确定与指令相关联的性能特征的监视代码或指令的操作的改变（例如，包括用于支持垃圾收集器的读取或写入屏障操作）。

4. 发明授权

US06751706B2 Multiple microprocessors with a shared cache 有权
标题翻译：具有共享缓存的多个微处理器
公开(公告)号：US06751706B2
公开(公告)日：2004-06-15
申请号：US09932651
申请日：2001-08-17
申请人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
IPC分类号： G06F1200
CPC分类号： G06F9/5011 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5094 , G06F11/3409 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885 , G06F2209/5014 , G06F2209/5021 , G06F2209/507 , G06F2212/1028 , G06F2212/681 , Y02D10/13 , Y02D10/16 , Y02D10/22 , Y02D10/24 , Y02D10/34
摘要： A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer. The L2 cache, along with all of the TLBs and &mgr;TLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task. Configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.
摘要翻译：数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。当L2缓存未命中时，访问L3内存中的数据的惩罚很高。该系统支持未命中错过，以使第二个错误中断一个段预取正在响应于第一个错过。因此，提供了一个可中断的SDRAM到L2缓存预取系统，其中错过了支持。为L2访问提供共享翻译后备缓冲器（TLB），而私有TLB与每个处理器相关联。微型TLB（muTLB）与可以启动存储器传输的每个资源相关联。 L2缓存以及所有TLB和muTLB都具有与每个条目关联的资源ID字段和任务ID字段，以允许基于资源或任务的冲洗和清理。提供配置电路以允许数字系统根据任务在任务上进行配置，以便降低功耗。

5. 发明授权

US08429383B2 Multi-processor computing system having a JAVA stack machine and a RISC-based processor 有权
标题翻译：具有JAVA堆栈机和基于RISC处理器的多处理器计算系统
公开(公告)号：US08429383B2
公开(公告)日：2013-04-23
申请号：US10631939
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F15/76
CPC分类号： G06F12/0253 , G06F9/30101 , G06F9/30174 , G06F9/3879 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/1036 , G06F12/126 , G06F2212/502 , G06F2212/681
摘要： A system comprises a first processor, a second processor coupled to the first processor, memory coupled to, and shared by, the first and second processors, and a synchronization unit coupled to the first and second processors. The second processor preferably comprises stack storage that resides in the core of the second processor. Further, the second processor executes stack-based instructions while the first processor executes one or more tasks including, for example, managing the memory via an operating system that executes only on the first processor. Associated methods are also disclosed.
摘要翻译：系统包括第一处理器，耦合到第一处理器的第二处理器，耦合到第一和第二处理器并由其共享的存储器，以及耦合到第一和第二处理器的同步单元。第二处理器优选地包括位于第二处理器的核心中的堆栈存储器。此外，第二处理器执行基于堆栈的指令，而第一处理器执行一个或多个任务，包括例如经由只在第一处理器上执行的操作系统来管理存储器。还公开了相关方法。

6. 发明授权

US07565385B2 Embedded garbage collection 有权
标题翻译：嵌入式垃圾收集
公开(公告)号：US07565385B2
公开(公告)日：2009-07-21
申请号：US10831387
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F17/00
CPC分类号： G06F12/0269 , Y02D10/13 , Y10S707/99957
摘要： An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded garbage collection object preferably uses control data to cause objects to be removed from said memory, the removed objects comprise those objects that were created while an embedded garbage collection object was active and that do not have references from root objects.
摘要翻译：电子系统包括处理器，耦合到处理器的存储器以及使嵌入式垃圾回收对象活动的应用编程接口。存储器存储一个或多个选择性地具有来自根对象的引用的对象。嵌入式垃圾回收对象优选地使用控制数据来使对象从所述存储器中移除，所移除的对象包括当嵌入式垃圾回收对象是活动的并且没有来自根对象的引用时创建的对象。

7. 发明授权

US07434021B2 Memory allocation in a multi-processor system 有权
标题翻译：多处理器系统中的内存分配
公开(公告)号：US07434021B2
公开(公告)日：2008-10-07
申请号：US10831388
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/5016 , Y02D10/22
摘要： A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.
摘要翻译：过程和相关系统包括基于控制输入在第一处理器中预分配存储器的一部分，并且在第二处理器中确定预分配存储器的部分是否可以满足存储器分配请求。此外，如果预先分配的存储器的一部分可以满足存储器分配请求，则该技术包括将存储器的预分配部分分配给分配请求。然而，如果预分配存储器的一部分不能满足存储器分配请求，则该技术包括将第一处理器中的存储器的一部分分配给分配请求。

8. 发明授权

US06996683B2 Cache coherency in a multi-processor system 有权
标题翻译：多处理器系统中的高速缓存一致性
公开(公告)号：US06996683B2
公开(公告)日：2006-02-07
申请号：US10632229
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F12/02
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/30174 , G06F9/3834 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transaction originating from the first processor, the first processor enables the second processor's coherence buffer, and information associated with the first processor's write transaction is stored in the second processor's coherence buffer to maintain data coherency between the first and second processors.
摘要翻译：一种系统包括具有高速缓冲存储器的第一处理器，具有高速缓冲存储器的第二处理器和可由第一处理器启用和禁用的相干缓冲器。该系统还包括耦合到第一和第二处理器的存储器子系统。对于来自第一处理器的写入事务，第一处理器启用第二处理器的相干缓冲器，并且与第一处理器的写入事务相关联的信息被存储在第二处理器的相干缓冲器中以维持第一和第二处理器之间的数据一致性。

9. 发明授权

US08032891B2 Energy-aware scheduling of application execution 有权
标题翻译：能源感知调度应用程序执行
公开(公告)号：US08032891B2
公开(公告)日：2011-10-04
申请号：US10151282
申请日：2002-05-20
申请人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
发明人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
IPC分类号： G06F9/46 , G06F1/32
CPC分类号： G06F9/4881 , G06F1/3228 , G06F1/329 , Y02D10/24
摘要： A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.
摘要翻译：移动设备（10）使用调度器（20）管理任务（18），用于在多个处理器（12）上调度任务。为了节约能源，要调度的任务集合分为两个（或多个）子集，根据不同的过程进行调度。在具体实施例中，第一子集基于执行任务的处理器包含具有最高能量消耗偏差的任务。该子集根据用于主要基于能量消耗标准的调度任务的功率感知程序进行调度。如果没有失败，则根据实时约束程序调度第二子集，该实时约束过程主要基于与第二子集中的各种任务相关联的期限来调度任务。如果任何一个过程都有故障，则能量消耗偏差最小的一个或多个任务从第一个子集移动到第二个子集，重复调度。

10. 发明授权

US07330937B2 Management of stack-based memory usage in a processor 有权
标题翻译：管理处理器中基于堆栈的内存使用情况
公开(公告)号：US07330937B2
公开(公告)日：2008-02-12
申请号：US10818584
申请日：2004-04-05
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/30047 , G06F9/3824 , G06F12/0802 , G06F12/126 , G06F2212/2515 , Y02D10/13
摘要： A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scratchpad memory depending on the determination. Other embodiments are disclosed herein as well.
摘要翻译：公开了一种方法，其包括确定数据子系统是作为高速缓存存储器还是作为暂存器存储器进行操作，其中从外部存储器取出的行被抑制并且编程控制位以使数据子系统作为高速缓存或暂存器存储器取决于决心。本文还公开了其它实施例。

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