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1. 发明授权

US06680542B1 Damascene structure having a metal-oxide-metal capacitor associated therewith 有权
标题翻译：具有与其相关联的金属氧化物 - 金属电容器的镶嵌结构
公开(公告)号：US06680542B1
公开(公告)日：2004-01-20
申请号：US09575214
申请日：2000-05-18
申请人： Gerald W. Gibson , Richard W. Gregor , Chun-Yung Sung , Daniel J. Vitkavage , Allen Yen
发明人： Gerald W. Gibson , Richard W. Gregor , Chun-Yung Sung , Daniel J. Vitkavage , Allen Yen
IPC分类号： H01L2348
CPC分类号： H01L28/40 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.
摘要翻译：本发明提供一种包括互连和电容器的半导体器件及其制造方法。该方法包括通过层间电介质层和位于层间电介质下面的电介质蚀刻停止层形成镶嵌互连结构，其中镶嵌互连结构接触第一互连结构。该方法还包括通过层间电介质层形成金属氧化物金属（MOM）电容器镶嵌结构，并终止在介电蚀刻停止层上。在替代实施例中，镶嵌结构可以是双镶嵌结构。此外，在另一个实施例中，镶嵌互连结构和MOM电容器可以构成较大集成电路的一部分。

2. 发明授权

US06346454B1 Method of making dual damascene interconnect structure and metal electrode capacitor 有权
标题翻译：制作双镶嵌互连结构和金属电极电容器的方法
公开(公告)号：US06346454B1
公开(公告)日：2002-02-12
申请号：US09383806
申请日：1999-08-26
申请人： Chun-Yung Sung , Allen Yen
发明人： Chun-Yung Sung , Allen Yen
IPC分类号： H01L21331
CPC分类号： H01L23/5223 , H01L21/31604 , H01L21/31612 , H01L21/3185 , H01L21/76807 , H01L21/76838 , H01L27/10844 , H01L27/10852 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device and method of making include an interconnect structure and a capacitor. The interconnect structure includes a metal line and a contact, and the capacitor includes upper and lower metal electrodes. The method includes forming a dielectric layer adjacent a semiconductor substrate, and simultaneously forming a first opening for the interconnect structure and a second opening for the capacitor, in the first dielectric layer. The method further includes selectively depositing a first conductive layer to fill the first opening to form the interconnect structure, and forming the upper and lower metal electrodes with a capacitor dielectric therebetween to form the capacitor in the second opening. The integrated circuit device provides a high-density capacitor having metal electrodes and which is compatible and integrated with dual damascene structures. As such, the capacitor is situated in a same level as a dual damascene interconnect structure.
摘要翻译：集成电路器件和制造方法包括互连结构和电容器。互连结构包括金属线和触点，并且电容器包括上下金属电极。该方法包括在第一电介质层中形成与半导体衬底相邻的电介质层，并且同时形成用于互连结构的第一开口和用于电容器的第二开口。该方法还包括选择性地沉积第一导电层以填充第一开口以形成互连结构，以及在其之间形成具有电容器电介质的上金属电极和下金属电极，以在第二开口中形成电容器。集成电路器件提供具有金属电极的高密度电容器，其与双镶嵌结构兼容并且集成。因此，电容器位于与双镶嵌互连结构相同的水平。

3. 发明授权

US06293847B1 Apparatus for chemical mechanical polishing endpoint detection using a hydrogen sensor 有权
标题翻译：使用氢传感器进行化学机械抛光终点检测的设备
公开(公告)号：US06293847B1
公开(公告)日：2001-09-25
申请号：US09418087
申请日：1999-10-14
申请人： William Graham Easter , John Albert Maze , Frank Miceli , Sudhanshu Misra , Allen Yen
发明人： William Graham Easter , John Albert Maze , Frank Miceli , Sudhanshu Misra , Allen Yen
IPC分类号： B24B5100
CPC分类号： B24B37/013 , B24B49/10 , G01B21/08 , G01N33/005
摘要： An apparatus for determining endpoint in the chemical mechanical polishing of a metal film using an acidic slurry includes a hydrogen sensor which senses the amount of hydrogen vapor being produced as a result of the reaction between the metal film and the acidic slurry. When the concentration of hydrogen vapor in the reaction area drops, endpoint is attained and the polishing operation may be terminated or otherwise adjusted. Hydrogen sensing elements include a palladium gate MOS transistor, expandable plastics and a tungsten oxide film.
摘要翻译：使用酸性浆料确定金属膜的化学机械抛光中的终点的装置包括氢传感器，其感测由于金属膜和酸性浆料之间的反应而产生的氢蒸汽的量。当反应区域中的氢蒸汽的浓度下降时，达到终点，并且可以终止或以其它方式调整抛光操作。氢传感元件包括钯栅极MOS晶体管，可膨胀塑料和氧化钨膜。

4. 发明授权

US07160799B2 Define via in dual damascene process 有权
标题翻译：通过双镶嵌工艺定义
公开(公告)号：US07160799B2
公开(公告)日：2007-01-09
申请号：US10603041
申请日：2003-06-24
申请人： Steven Alan Lytle , Thomas Michael Wolf , Allen Yen
发明人： Steven Alan Lytle , Thomas Michael Wolf , Allen Yen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76813 , H01L23/528 , H01L23/538 , H01L2924/0002 , H01L2924/00
摘要： The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.
摘要翻译：本发明包括一种用于制造集成电路的方法，包括在导电材料上提供包括电介质层的衬底，在电介质层上沉积硬掩模，在硬掩模上施加第一光致抗蚀剂并对光栅定义沟槽，蚀刻硬掩模并部分地蚀刻电介质以形成具有底部的沟槽，剥离光致抗蚀剂，施加第二光致抗蚀剂并且在沟槽之间照明定义狭缝，从沟槽的底部选择性地蚀刻电介质到下面的导电材料。硬掩模和第二光致抗蚀剂均用作掩模。之后，形成与底层金属的连接，由此形成集成电路。

5. 发明授权

US06838717B1 Stacked structure for parallel capacitors and method of fabrication 有权
标题翻译：并联电容器的堆叠结构及其制造方法
公开(公告)号：US06838717B1
公开(公告)日：2005-01-04
申请号：US09653295
申请日：2000-08-31
申请人： Allen Yen , Frank Yauchee Hui , Yifeng Winston Yan
发明人： Allen Yen , Frank Yauchee Hui , Yifeng Winston Yan
IPC分类号： H01L23/52 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/04 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A monolithic integrated circuit including a capacitor structure. In one embodiment the integrated circuit includes at least first and second levels of interconnect conductor for connection to a semiconductor layer and a stack of alternating conductive and insulative layers formed in vertical alignment with respect to an underlying plane. The stack is formed between the first and second levels of conductor. Preferably the stack includes a first conductive layer, a first insulator layer formed over the first conductive layer, a second conductive layer formed over the first insulative layer, a second insulator layer formed over the second conductive layer, and a third conductive layer formed over the second insulative layer, with the first and third conductive layers commonly connected.
摘要翻译：包括电容器结构的单片集成电路。在一个实施例中，集成电路包括用于连接到半导体层的至少第一和第二级别的互连导体以及相对于下面的平面垂直对准地形成的交替导电层和绝缘层的叠层。堆叠形成在第一和第二层导体之间。优选地，堆叠包括第一导电层，形成在第一导电层上的第一绝缘体层，形成在第一绝缘层上的第二导电层，形成在第二导电层上的第二绝缘体层，以及形成在第二导电层上的第三导电层第二绝缘层，第一和第三导电层共同连接。

6. 发明授权

US06657302B1 Integration of low dielectric material in semiconductor circuit structures 有权
标题翻译：低电介质材料在半导体电路结构中的集成
公开(公告)号：US06657302B1
公开(公告)日：2003-12-02
申请号：US09464811
申请日：1999-12-17
申请人： Huili Shao , Susan Clay Vitkavage , Allen Yen
发明人： Huili Shao , Susan Clay Vitkavage , Allen Yen
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating integrated circuits with improved electrical performance. The structure comprises electronic devices formed along a semiconductor surface, a first upper level of interconnect members over the semiconductor surface, a lower level of interconnect members formed between the semiconductor surface and the first upper level, and insulative material positioned to electrically isolate portions of the upper level of interconnect members from one another. The insulative material comprises a continuous layer extending from within regions between members of the upper interconnect level to within regions between members of the lower interconnect level and is characterized by a dielectric constant less than 3.9. The method begins with a semiconductor layer having electronic device regions thereon. A first insulative layer is deposited over the electronic device regions and a lower level of interconnect members is formed over the first insulative layer. A second insulative layer is formed between and over lower level interconnect members and an upper level of interconnect members is formed over the second insulative layer. Portions of the second insulative layer positioned between interconnect members of the lower and upper levels are removed and a third insulative layer is formed in regions from which the second insulative layer is removed.
摘要翻译：一种用于制造具有改善的电性能的集成电路的结构和方法。该结构包括沿着半导体表面形成的电子器件，半导体表面上的第一上层互连构件，形成在半导体表面和第一上层和绝缘材料定位成将上部互连构件的一部分彼此电隔离。绝缘材料包括从上部互连层的构件之间的区域内延伸到下部互连层的构件之间的区域内的连续层，其特征在于介电常数小于3.9.该方法从具有电子器件区域的半导体层开始上。在电子器件区域上沉积第一绝缘层，并且在第一绝缘层上形成较低级别的互连构件。第二绝缘层形成在下层互连构件之间和之上，并且互连构件的上层形成在第二绝缘层上。位于下层和上层的互连构件之间的第二绝缘层的部分被去除，并且在去除第二绝缘层的区域中形成第三绝缘层。

7. 发明授权

US06194323B1 Deep sub-micron metal etch with in-situ hard mask etch 有权
标题翻译：深亚微米金属蚀刻与原位硬掩模蚀刻
公开(公告)号：US06194323B1
公开(公告)日：2001-02-27
申请号：US09212228
申请日：1998-12-16
申请人： Stephen Ward Downey , Allen Yen
发明人： Stephen Ward Downey , Allen Yen
IPC分类号： H01L2100
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/32136
摘要： The invention includes a process for the production of semiconductor devices comprising the steps of depositing a metal layer on a semiconductor substrate, depositing a hardmask layer on said metal layer, depositing a photoresist on said hardmask layer, patterning said photoresist, thereby exposing and patterning portions of said hardmask layer, etching said exposed portions of said hardmask layer with a hardmask etchant, thereby exposing and patterning portions of said metal layer, removing, or not, said photoresist, and etching said exposed portions of said metal layer with a metal etchant and semiconductor devices made by said process.
摘要翻译：本发明包括一种用于制造半导体器件的方法，包括以下步骤：在半导体衬底上沉积金属层，在所述金属层上沉积硬掩模层，在所述硬掩模层上沉积光致抗蚀剂，图案化所述光致抗蚀剂，由此曝光和图形化部分的所述硬掩模层，用硬掩模蚀刻剂蚀刻所述硬掩模层的所述暴露部分，从而暴露和图案化所述金属层的部分，去除或不去除所述光致抗蚀剂，并用金属蚀刻剂蚀刻所述金属层的所述暴露部分，由所述方法制造的半导体器件。

8. 发明申请

US20050067710A1 Define via in dual damascene process 有权
标题翻译：通过双镶嵌工艺定义
公开(公告)号：US20050067710A1
公开(公告)日：2005-03-31
申请号：US10603041
申请日：2003-06-24
申请人： Steven Lytle , Thomas Wolf , Allen Yen
发明人： Steven Lytle , Thomas Wolf , Allen Yen
IPC分类号： H01L21/768 , H01L23/528 , H01L23/538 , H01L23/48 , H01L21/4763 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76811 , H01L21/76813 , H01L23/528 , H01L23/538 , H01L2924/0002 , H01L2924/00
摘要： The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.
摘要翻译：本发明包括一种用于制造集成电路的方法，包括在导电材料上提供包括电介质层的衬底，在电介质层上沉积硬掩模，在硬掩模上施加第一光致抗蚀剂并对光栅定义沟槽，蚀刻硬掩模并部分地蚀刻电介质以形成具有底部的沟槽，剥离光致抗蚀剂，施加第二光致抗蚀剂并且在沟槽之间照明定义狭缝，从沟槽的底部选择性地蚀刻电介质到下面的导电材料。硬掩模和第二光致抗蚀剂均用作掩模。之后，形成与底层金属的连接，由此形成集成电路。

9. 发明授权

US06559062B1 Method for avoiding notching in a semiconductor interconnect during a metal etching step 有权
标题翻译：一种用于在金属蚀刻步骤期间避免半导体互连中的切口的方法
公开(公告)号：US06559062B1
公开(公告)日：2003-05-06
申请号：US09713504
申请日：2000-11-15
申请人： Stephen Ward Downey , Allen Yen , Thomas Michael Wolf , Paul B. Murphey
发明人： Stephen Ward Downey , Allen Yen , Thomas Michael Wolf , Paul B. Murphey
IPC分类号： H01L21461
CPC分类号： H01L21/31116 , H01L21/32136
摘要： A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in the side (30) of the interconnect. A reactive ion etching process (118) used to remove portions of a metal layer (16) to form the interconnect includes a burst etch step (108) wherein a first high flow rate (48) of passivation gas is delivered, followed by a main metal etch step (110) wherein the flow rate of passivation gas is reduced to a second lower value.
摘要翻译：一种在半导体器件（82）中使用厚度（T）不大于0.66微米的光致抗蚀剂层（20）形成金属互连（102）的工艺（100），而不在侧面（30）中形成缺口互连。用于去除金属层（16）的部分以形成互连的反应离子蚀刻工艺（118）包括突发蚀刻步骤（108），其中递送钝化气体的第一高流速（48），随后是主体金属蚀刻步骤（110），其中钝化气体的流速降低到第二较低值。

10. 发明授权

US06506673B2 Method of forming a reverse gate structure with a spin on glass process 有权
标题翻译：用旋转玻璃工艺形成反向栅极结构的方法
公开(公告)号：US06506673B2
公开(公告)日：2003-01-14
申请号：US09878690
申请日：2001-06-11
申请人： Yi Ma , Huili Shao , Joseph A. Taylor , Allen Yen
发明人： Yi Ma , Huili Shao , Joseph A. Taylor , Allen Yen
IPC分类号： H01L214763
CPC分类号： H01L29/66545
摘要： The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.
摘要翻译：本发明提供了一种方法，其包括在半导体衬底上限定包括玻璃上的旋转玻璃的虚拟栅极结构，在所述虚拟栅极结构上形成介电层，去除所述伪栅极结构以在所述电介质层内形成栅极开口，以及形成栅极材料，其在栅极开口内包括金属。

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