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    • 1. 发明授权
    • Method and apparatus for automatic exposure control using localized capacitive coupling in a matrix-addressed imaging panel
    • 用于在矩阵寻址的成像面板中使用局部电容耦合的自动曝光控制的方法和装置
    • US06404851B1
    • 2002-06-11
    • US09537485
    • 2000-03-30
    • George Edward PossinRobert Gideon WodnickiSung Su Han
    • George Edward PossinRobert Gideon WodnickiSung Su Han
    • H05G138
    • H04N5/353A61B6/4233G01T1/2928H04N5/2351H04N5/32
    • A method and system for an automatic exposure control (AEC) arrangement for a matrix-addressed imaging panel having an array of sensors including use of localized regions of the imaging panel exhibiting capacitive coupling. In one embodiment, the matrix-addressed imaging panel includes one or more AEC electrode receptive field regions that provide a signal representative of exposure specific, respective AEC electrode receptive field regions. Additionally, in another embodiment, the imaging array includes data line signal monitoring regions in which capacitive coupling between electrodes in radiation sensors adjacent to the data line are read and processed to provide and AEC signal. In another embodiment, the imaging array includes both AEC electrode filed receptive regions and data line signal monitoring regions that are coupled to an AEC controller for control of the radiation source for the imaging array.
    • 一种用于矩阵寻址成像面板的自动曝光控制(AEC)装置的方法和系统,其具有包括使用成像面板的局部区域呈现电容耦合的传感器阵列。 在一个实施例中,矩阵寻址的成像面板包括一个或多个AEC电极接收场区域,其提供表示曝光特定的相应AEC电极接收场区域的信号。 此外,在另一个实施例中,成像阵列包括数据线信号监测区域,其中与数据线相邻的辐射传感器中的电极之间的电容耦合被读取和处理以提供和AEC信号。 在另一个实施例中,成像阵列包括耦合到AEC控制器的AEC电极接收区域和数据线信号监测区域,用于控制用于成像阵列的辐射源。
    • 7. 发明授权
    • Method and apparatus for controlling scanning of mosaic sensor array
    • 用于控制马赛克传感器阵列扫描的方法和装置
    • US07313053B2
    • 2007-12-25
    • US10978012
    • 2004-10-29
    • Robert Gideon Wodnicki
    • Robert Gideon Wodnicki
    • H04R17/00G01S7/521
    • B06B1/0625A61B8/13B06B1/0292H03K17/102H03K17/6874
    • A scanning architecture that makes it possible to update only those ultrasonic transducer subelements of a mosaic transducer array that change from view to view. The configuration of the switch matrix is fully programmable. The switch matrix includes access switches that connect subelements to bus lines and matrix switches that connect subelements to subelements. Each subelement has a unit switch cell associated therewith, each unit switch cell comprising at least one access switch, at least one matrix switch, and addressing and control logic. Optionally, each unit switch cell also includes latches for storing the future switch states of the switches to be programmed. The switches themselves have memory for storing their current switch states.
    • 扫描架构,使得只能更新马赛克换能器阵列的从视图变化到视图的那些超声换能器子元件成为可能。 开关矩阵的配置是完全可编程的。 开关矩阵包括将子元件连接到总线线路的接入开关和将子元件连接到子元件的矩阵开关。 每个子元件具有与其相关联的单元开关单元,每个单元开关单元包括至少一个存取开关,至少一个矩阵开关以及寻址和控制逻辑。 可选地,每个单元开关单元还包括用于存储要编程的开关的未来开关状态的锁存器。 开关本身具有用于存储其当前开关状态的存储器。
    • 8. 发明授权
    • Integrated high-voltage switching circuit for ultrasound transducer array
    • 用于超声换能器阵列的集成高压开关电路
    • US06956426B2
    • 2005-10-18
    • US10988024
    • 2004-11-12
    • Robert Gideon Wodnicki
    • Robert Gideon Wodnicki
    • A61B8/00H03K17/10H03K17/687H03K17/16
    • H03K17/102H03K17/6874
    • An integrated high-voltage switching circuit includes a switch having ON and OFF states and having a parasitic gate capacitance. The switch consists of a pair of DMOS transistors integrated back to back and having a shared gate terminal, the drains of the DMOS transistors being connected to the input and output terminals of the switch respectively. The switching circuit further includes a turn-on circuit comprising a PMOS transistor having its drain connected to the shared gate terminal of the switch via a first diode, having its source connected to a global switch gate bias voltage terminal from which the PMOS transistor draws current, and having its gate electrically coupled to a switch gate control terminal that receives a switch gate control voltage input. The switch transitions from the OFF state to the ON state in response to a first transition of the switch gate control voltage input that causes the PMOS transistor to turn on, and the switch remains in the ON state in response to a second transition of the switch gate control voltage input that causes the PMOS transistor to turn off. The DMOS transistors turn on in response to the shared gate being coupled to the switch gate bias voltage when the PMOS transistor turns on.
    • 集成的高压开关电路包括具有ON和OFF状态并具有寄生栅极电容的开关。 开关由一对背对背集成的DMOS晶体管组成,具有共用栅极端子,DMOS晶体管的漏极分别连接到开关的输入和输出端子。 开关电路还包括导通电路,其包括PMOS晶体管,其PMOS的漏极经由第一二极管连接到开关的共享栅极端子,其源极连接到全局开关栅极偏置电压端子,PMOS晶体管从该栅极偏置电压端子吸取电流 并且其栅极电耦合到接收开关栅极控制电压输入的开关栅极控制端子。 响应于导致PMOS晶体管导通的开关栅极控制电压输入的第一跃迁,开关从OFF状态转变到ON状态,并且开关响应于开关的第二过渡而保持在ON状态 栅极控制电压输入使PMOS晶体管关断。 当PMOS晶体管导通时,DMOS晶体管响应于共享栅极耦合到开关栅极偏置电压而导通。
    • 9. 发明授权
    • Modular turbo decoder for expanded code word length
    • 用于扩展码字长度的模块化turbo解码器
    • US06594792B1
    • 2003-07-15
    • US09561333
    • 2000-04-28
    • Stephen Michael HladikAbdallah Mahmoud ItaniNick Andrew Van StralenRobert Gideon WodnickiJohn Anderson Fergus Ross
    • Stephen Michael HladikAbdallah Mahmoud ItaniNick Andrew Van StralenRobert Gideon WodnickiJohn Anderson Fergus Ross
    • H03M1329
    • H03M13/3905H03M13/2957H03M13/3933H03M13/3972
    • A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data-rate capability of the turbo decoder system. Input data samples are provided to an interleaver/de-interleaver module wherein they are divided into segments of predetermined size, each segment being provided to a respective turbo decoder module. The outputs of each turbo decoder module are a posteriori probabilities which are re-ordered in the interleaver/de-interleaver module, segmented, and provided back to the turbo decoders as a priori information-bit probabilities. For the case of a turbo code comprising two component codes, the a posteriori information-bit probabilities are re-ordered according to the interleaver definition at the end of odd-numbered half iterations, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of iterations have been performed. Data decisions are made on the final a posteriori bit probability estimates.
    • 利用MAP解码算法的turbo解码器系统具有预定数量的turbo解码器模块,用于并行地解码turbo码分量码字的段,从而扩展turbo解码器系统的块长度和数据速率能力。 将输入数据样本提供给交织器/解交织器模块,其中它们被划分成预定大小的段,每个段被提供给相应的turbo解码器模块。 每个turbo解码器模块的输出是在交织器/解交织器模块中重排序的后验概率,被分段并作为先验信息比特概率返回给turbo解码器。 对于包括两个分量代码的turbo码的情况,根据奇数半迭代结束时的交织器定义重新排序后验信息比特概率,而在偶数半迭代结束时,它们 根据解交织器定义重新排序。 解码继续,直到执行所需的迭代次数。 对最终的后验位概率估计作出数据决定。
    • 10. 发明授权
    • Tileable sensor array
    • 可分层传感器阵列
    • US08659148B2
    • 2014-02-25
    • US12956194
    • 2010-11-30
    • John Eric TkaczykLowell Scott SmithCharles Edward BaumgartnerRobert Gideon WodnickiRayette Ann FisherCharles Gerard WoychikRobert Stephen Lewandowski
    • John Eric TkaczykLowell Scott SmithCharles Edward BaumgartnerRobert Gideon WodnickiRayette Ann FisherCharles Gerard WoychikRobert Stephen Lewandowski
    • H01L23/34
    • H01L27/20A61B8/4483H01L27/14634H01L27/14658H01L2224/16225H01L2924/01322H01L2924/1461H01L2924/00
    • A method for forming a tileable detector array is presented. The method includes forming a detector module, where forming the detector module includes providing a sensor array having a first side and a second side, where the sensor array includes a first plurality of contact pads disposed on the second side of the sensor array, disposing the sensor array on an interconnect layer, where the interconnect layer includes a redistribution layer having a first side and a second side, where the redistribution layer includes a second plurality of contact pads disposed on the first side, an integrated circuit having a plurality of through vias disposed therethrough, where a first side of the integrated circuit is operationally coupled to the second side of the redistribution layer, where the sensor array is disposed on the interconnect layer such that the first plurality of contact pads on the second side of the sensor array are aligned with the second plurality of contact pads on the first side of the redistribution layer, operationally coupling the first plurality of contact pads on the second side of the sensor array to the second plurality of contact pads on the redistribution layer to form a sensor stack, coupling the sensor stack to a substrate to form the detector module, and tiling a plurality of detector modules on a second substrate to form the tileable detector array.
    • 提出了一种形成可瓦片检测器阵列的方法。 该方法包括形成检测器模块,其中形成检测器模块包括提供具有第一侧和第二侧的传感器阵列,其中传感器阵列包括设置在传感器阵列的第二侧上的第一组多个接触垫, 传感器阵列,其中所述互连层包括具有第一侧和第二侧的再分配层,其中所述再分布层包括设置在所述第一侧上的第二多个接触焊盘,具有多个通孔的集成电路 其中集成电路的第一侧可操作地耦合到再分布层的第二侧,其中传感器阵列设置在互连层上,使得传感器阵列的第二侧上的第一组多个接触焊盘是 与再分配层的第一侧上的第二多个接触焊盘对准,可操作地连接冷杉 传感器阵列的第二侧上的多个接触焊盘连接到再分配层上的第二多个接触焊盘,以形成传感器堆叠,将传感器堆叠耦合到衬底以形成检测器模块,并且平铺多个检测器模块 在第二基板上形成可瓦片检测器阵列。