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1. 发明授权

US07391245B2 Delay locked loop and method for setting a delay chain 有权
标题翻译：延迟锁定循环和设置延迟链的方法
公开(公告)号：US07391245B2
公开(公告)日：2008-06-24
申请号：US11437825
申请日：2006-05-22
申请人： Patrick Heyne , Aaron Nygren
发明人： Patrick Heyne , Aaron Nygren
IPC分类号： H03L7/06
CPC分类号： H03K5/133 , H03K2005/00058
摘要： A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via the delay chain depending on the number of delay cells in the series that are activated for delay. The phase detector arrangement detects the phase of the signal at the output of each delay cell in the delay chain. The control unit activates a number Z of the delay cells of the delay chain based on the difference in phase of the original signal and the delayed signal.
摘要翻译：延迟锁定环包括包含多个串联延迟单元的延迟链，包含多个相位检测器单元的相位检测器装置和控制单元。延迟锁定环路根据延迟激活的串联中的延迟单元的数量，经由延迟链将输入信号延迟延迟时间。相位检测器装置检测延迟链中每个延迟单元的输出处的信号的相位。控制单元基于原始信号和延迟信号的相位差来激活延迟链的延迟单元的数量Z。

2. 发明申请

US20060214709A1 Circuit arrangement for generating a synchronization signal 审中-公开
标题翻译：用于产生同步信号的电路装置
公开(公告)号：US20060214709A1
公开(公告)日：2006-09-28
申请号：US11375569
申请日：2006-03-15
申请人： Aaron Nygren , Patrick Heyne
发明人： Aaron Nygren , Patrick Heyne
IPC分类号： H03L7/06
CPC分类号： H04L7/0337
摘要： A circuit arrangement is provided for generating a synchronization signal having signal edge changes whose timings are defined. The arrangement includes a plurality of controllable signal delay arrangements, each including a circuit part with variable signal delay and a circuit part with constant signal delay, where an input signal is supplied to a first controllable signal delay arrangement, a phase detection device including two inputs and one output, and a control circuit that controls the circuit parts with variable signal delay. The input of the control circuit is connected to the output of the phase detection device, and the output of the control circuit is connected to control inputs of the circuit parts with variable signal delay. The input signal is also supplied to the first input of the phase detection device. One output of one of the controllable signal delay arrangements is connected to the second input of the phase detection device. At least one of the controllable signal delay arrangements produces a synchronization signal at the output of the circuit part with variable signal delay.
摘要翻译：提供了一种电路装置，用于产生具有定义其定时的信号沿变化的同步信号。该装置包括多个可控信号延迟装置，每个可控信号延迟装置包括具有可变信号延迟的电路部分和具有恒定信号延迟的电路部分，其中输入信号被提供给第一可控信号延迟装置，相位检测装置包括两个输入和一个输出，以及控制电路，其具有可变的信号延迟。控制电路的输入端连接到相位检测装置的输出端，控制电路的输出端与可变信号延迟的电路部分的控制输入相连。输入信号也被提供给相位检测装置的第一输入端。可控信号延迟装置之一的一个输出端连接到相位检测装置的第二输入端。可控信号延迟装置中的至少一个在具有可变信号延迟的电路部分的输出处产生同步信号。

3. 发明申请

US20060273834A1 Delay locked loop and method for setting a delay chain 有权
标题翻译：延迟锁定循环和设置延迟链的方法
公开(公告)号：US20060273834A1
公开(公告)日：2006-12-07
申请号：US11437825
申请日：2006-05-22
申请人： Patrick Heyne , Aaron Nygren
发明人： Patrick Heyne , Aaron Nygren
IPC分类号： H03L7/06
CPC分类号： H03K5/133 , H03K2005/00058
摘要： A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via the delay chain depending on the number of delay cells in the series that are activated for delay. The phase detector arrangement detects the phase of the signal at the output of each delay cell in the delay chain. The control unit activates a number Z of the delay cells of the delay chain based on the difference in phase of the original signal and the delayed signal.
摘要翻译：延迟锁定环包括包含多个串联延迟单元的延迟链，包含多个相位检测器单元的相位检测器装置和控制单元。延迟锁定环路根据延迟激活的串联中的延迟单元的数量，经由延迟链将输入信号延迟延迟时间。相位检测器装置检测延迟链中每个延迟单元的输出处的信号的相位。控制单元基于原始信号和延迟信号的相位差来激活延迟链的延迟单元的数量Z。

4. 发明申请

US20070182470A1 Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal 有权
标题翻译：用于同步时钟信号的装置和方法以及调整时钟信号的占空比
公开(公告)号：US20070182470A1
公开(公告)日：2007-08-09
申请号：US11497848
申请日：2006-08-02
申请人： Patrick Heyne
发明人： Patrick Heyne
IPC分类号： H03L7/06
CPC分类号： G06F1/10 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C11/4076 , H03L7/0814 , H03L7/087
摘要： A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal, and a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.
摘要翻译：公开了一种用于使输入时钟信号与输出时钟信号同步的装置。一个实施例包括用于控制馈送到第一延迟的时钟信号的边缘的双稳态触发电路，用于确定延迟第一延迟的第一时钟信号与输入时钟信号之间的相位的第二相位比较器，以及第二控制器用于控制与由第二相位比较器确定的相位对应的第一时钟信号的延迟。

5. 发明申请

US20050270852A1 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US20050270852A1
公开(公告)日：2005-12-08
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

6. 发明申请

US20050253638A1 Method and circuit arrangement for resetting an integrated circuit 有权
标题翻译：用于复位集成电路的方法和电路装置
公开(公告)号：US20050253638A1
公开(公告)日：2005-11-17
申请号：US11117736
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
IPC分类号： G06F1/24 , G11C5/14 , G11C11/4072 , H01L21/82 , H03K5/1534 , H03L7/00
CPC分类号： G06F1/24 , H03K5/1534
摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.
摘要翻译：本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

7. 发明授权

US06806752B2 Method and logic/memory module for correcting the duty cycle of at least one control/reference signal 有权
标题翻译：用于校正至少一个控制/参考信号的占空比的方法和逻辑/存储器模块
公开(公告)号：US06806752B2
公开(公告)日：2004-10-19
申请号：US10340046
申请日：2003-01-10
申请人： Patrick Heyne
发明人： Patrick Heyne
IPC分类号： G06F104
CPC分类号： H03K5/1565 , H03K5/06
摘要： A method and logic/memory module set the desired corrected duty cycle between the time periods of the first and second level states of at least one control/reference signal. In that, the rising time period of the rising edge and/or the fall time period of the falling edge of the control/reference signal are increased and/or decreased (i.e. changed) by a predefinable correction time period.
摘要翻译：方法和逻辑/存储器模块在至少一个控制/参考信号的第一和第二电平状态的时间周期之间设置期望的校正占空比。因此，控制/参考信号的下降沿的上升沿和/或下降时间周期的上升时间周期增加和/或减小（即改变）预定的校正时间段。

8. 发明授权

US06480024B2 Circuit configuration for programming a delay in a signal path 有权
公开(公告)号：US06480024B2
公开(公告)日：2002-11-12
申请号：US10046395
申请日：2001-10-19
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
IPC分类号： H03K190173
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00091
摘要： A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

9. 发明授权

US06469563B2 Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals 有权
标题翻译：电路配置，用于补偿两个输入信号之间的运行时间和脉冲占空比因子差异
公开(公告)号：US06469563B2
公开(公告)日：2002-10-22
申请号：US09865752
申请日：2001-05-25
申请人： Patrick Heyne , Thoai-Thai Le
发明人： Patrick Heyne , Thoai-Thai Le
IPC分类号： G06G712
CPC分类号： H03K5/1252 , H03K5/13 , H03K5/26
摘要： The circuit configuration compensates runtime and pulse-duty-factor differences of two input signals having approximately equal frequency and phase. For each input signal respectively present at an input of the circuit configuration, a signal path is provided that, dependent on the state of the output, is influenced in such a way that the output signal follows the input signal that changes first. A feedback branch with a time-delay element feeds back the output signal to the inputs with a delay, in such a way that these inputs are prepared for the next change of input signal. The delay time of the time-delay element is greater than the maximum chronological deviation between the two input signals.
摘要翻译：电路配置补偿具有大致相同频率和相位的两个输入信号的运行时间和脉冲占空比因子差异。对于分别存在于电路配置的输入端的每个输入信号，提供信号路径，其取决于输出的状态受到影响，使得输出信号遵循首先改变的输入信号。具有时间延迟元件的反馈分支以这样的方式将输出信号反馈到输入端，使得这些输入被准备用于输入信号的下一个改变。时间延迟元件的延迟时间大于两个输入信号之间的最大时间顺序偏差。

10. 发明授权

US06307416B1 Integrated circuit for producing two output clock signals at levels which do not overlap in time 有权
标题翻译：用于产生两个输出时钟信号的集成电路，其电平在时间上不重叠
公开(公告)号：US06307416B1
公开(公告)日：2001-10-23
申请号：US09519541
申请日：2000-03-06
申请人： Patrick Heyne , Thoralf Graëtz , Dieter Härle
发明人： Patrick Heyne , Thoralf Graëtz , Dieter Härle
IPC分类号： H03H1116
CPC分类号： H03K5/1515 , H03K3/356113
摘要： The integrated circuit has two inputs each supplying one input clock. Two outputs each output one output clock. The first logic levels of the output clock signals at the outputs do not overlap in time.
摘要翻译：集成电路具有两个输入，每个输入提供一个输入时钟。两个输出端输出一个输出时钟。输出端的输出时钟信号的第一个逻辑电平在时间上不重叠。

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