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1. 发明申请

US20110141816A1 Tracking Cells For A Memory System 有权
标题翻译：跟踪记忆系统的单元格
公开(公告)号：US20110141816A1
公开(公告)日：2011-06-16
申请号：US13031041
申请日：2011-02-18
申请人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Read operations are performed on the tracking cells, where threshold voltages of physical states of the tracking cells are further apart than threshold voltages of physical states of non-tracking cells. Based on the read operations, an extent to which the tracking cells are errored is determined.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。在跟踪单元上执行读操作，其中跟踪单元的物理状态的阈值电压比非跟踪单元的物理状态的阈值电压更远。基于读取操作，确定跟踪单元被错误的程度。

2. 发明授权

US07681094B2 Data recovery in a memory system using tracking cells 有权
标题翻译：使用跟踪单元的存储系统中的数据恢复
公开(公告)号：US07681094B2
公开(公告)日：2010-03-16
申请号：US11752024
申请日：2007-05-22
申请人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
IPC分类号： G11C29/00 , G06F13/00
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

3. 发明授权

US07760555B2 Tracking cells for a memory system 有权
标题翻译：跟踪单元格的内存系统
公开(公告)号：US07760555B2
公开(公告)日：2010-07-20
申请号：US11752008
申请日：2007-05-22
申请人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

4. 发明授权

US08072817B2 Tracking cells for a memory system 有权
标题翻译：跟踪单元格的内存系统
公开(公告)号：US08072817B2
公开(公告)日：2011-12-06
申请号：US13031041
申请日：2011-02-18
申请人： Daniel C Guterman , Stephen J Gross , Shahzad Khalid , Geoffrey S Gongwer
发明人： Daniel C Guterman , Stephen J Gross , Shahzad Khalid , Geoffrey S Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Read operations are performed on the tracking cells, where threshold voltages of physical states of the tracking cells are further apart than threshold voltages of physical states of non-tracking cells. Based on the read operations, an extent to which the tracking cells are errored is determined.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。在跟踪单元上执行读操作，其中跟踪单元的物理状态的阈值电压比非跟踪单元的物理状态的阈值电压更远。基于读取操作，确定跟踪单元被错误的程度。

5. 发明授权

US07237074B2 Tracking cells for a memory system 有权
标题翻译：跟踪单元格的内存系统
公开(公告)号：US07237074B2
公开(公告)日：2007-06-26
申请号：US10461244
申请日：2003-06-13
申请人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen J. Gross , Shahzad Khalid , Geoffrey S. Gongwer
IPC分类号： G12F12/00
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

6. 发明授权

US06486715B2 System and method for achieving fast switching of analog voltages on large capacitive load 有权
标题翻译：在大电容负载下实现模拟电压的快速切换的系统和方法
公开(公告)号：US06486715B2
公开(公告)日：2002-11-26
申请号：US09825615
申请日：2001-04-02
申请人： Geoffrey S. Gongwer , Shahzad Khalid
发明人： Geoffrey S. Gongwer , Shahzad Khalid
IPC分类号： H03K17687
CPC分类号： G11C5/145 , G11C8/08
摘要： Driver (100) and method are provided for driving capacitive load (120) that achieve an improved response time without increasing power consumption of the driver. Driver (100) has load buffer (105) with an input (110) for receiving an input voltage (VIN), and an output 115 for coupling an output voltage (VOUT) to load 120. VOUT is driven between a first voltage level (V1) and a second voltage level (V2) in response to changes in VIN. Driver (100) also has reserve circuit (125) with capacitor (130), reserve buffer (135), switch (140) for coupling the capacitor to capacitive load (120) and controller (145) for operating the switch. Reserve buffer (135) has an input (150) for receiving an input voltage (VRES—IN), and an output (155) for coupling an output voltage (VRES—OUT) to capacitor (130) to charge the capacitor. Controller (145) is configured to operate switch (140) to couple capacitor (130) to capacitive load (120) when VOUT is being driven between V1 and V2.
摘要翻译：驱动器（100）和方法被提供用于驱动电容性负载（120），其实现改善的响应时间，而不增加驱动器的功率消耗。驱动器（100）具有负载缓冲器（105），其具有用于接收输入电压（VIN）的输入端（110）和用于将输出电压（VOUT）耦合到负载120的输出端115.VOUT在第一电压电平 V1）和响应于VIN变化的第二电压电平（V2）。驱动器（100）还具有用于将电容器耦合到电容性负载（120）的开关（140）和用于操作开关的控制器（145）的具有电容器（130），保留缓冲器（135）的开关（140）。保留缓冲器（135）具有用于接收输入电压（VRES-IN）的输入端（150）和用于将输出电压（VRES-OUT）耦合到电容器（130）以对电容器充电的输出端（155）。当VOUT在V1和V2之间被驱动时，控制器（145）被配置为操作开关（140）以将电容器（130）耦合到电容性负载（120）。

7. 发明授权

US07447079B2 Method for sensing negative threshold voltages in non-volatile storage using current sensing 有权
标题翻译：使用电流检测来检测非易失性存储器中的负阈值电压的方法
公开(公告)号：US07447079B2
公开(公告)日：2008-11-04
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

8. 发明申请

US20070297234A1 Non-Volatile Memory And Method With Bit Line To Bit Line Coupled Compensation 有权
标题翻译：非易失性存储器和位线对位线耦合补偿方法
公开(公告)号：US20070297234A1
公开(公告)日：2007-12-27
申请号：US11848385
申请日：2007-08-31
申请人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
发明人： Raul-Adrian Cernea , Yan Li , Mehrdad Mofidi , Shahzad Khalid
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C16/3468
摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
摘要翻译：当编程连续的存储器单元页面时，每当存储器存储单元已经达到其目标状态并被编程禁止或被锁定以进一步编程时，它在仍在编程的相邻存储器存储单元上产生扰动。本发明提供了编程电路和方法的一部分，其中将扰动的偏移量添加到仍在编程中的相邻存储器存储单元中。偏移量通过程序禁止存储器存储单元的相邻位线与静止在编程存储器存储单元之间的受控耦合相加。以这种方式，消除或最小化并行高密度存储器存储单元中编程中固有的错误。

9. 发明申请

US20060140007A1 Non-volatile memory and method with shared processing for an aggregate of read/write circuits 审中-公开
标题翻译：非易失性存储器和具有用于读/写电路的集合的共享处理的方法
公开(公告)号：US20060140007A1
公开(公告)日：2006-06-29
申请号：US11026536
申请日：2004-12-29
申请人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Chan
发明人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Chan
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。处理器由输入逻辑，锁存器和输出逻辑实现。输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

10. 发明申请

US20050169051A1 Writable tracking cells 有权
标题翻译：可追踪单元格
公开(公告)号：US20050169051A1
公开(公告)日：2005-08-04
申请号：US11064529
申请日：2005-02-22
申请人： Shahzad Khalid , Daniel Guterman , Geoffrey Gongwer , Richard Simko , Kevin Conley
发明人： Shahzad Khalid , Daniel Guterman , Geoffrey Gongwer , Richard Simko , Kevin Conley
IPC分类号： G11C7/06 , G11C7/14 , G11C11/34 , G11C11/56 , G11C27/00
CPC分类号： G11C7/14 , G11C7/06 , G11C11/5642 , G11C27/005 , G11C2211/5634
摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.
摘要翻译：本发明提出了使用可写跟踪单元的几种技术。为存储器的每个写入块提供多个跟踪单元。每当相关联的写入块的用户单元被优选地同时使用相同的固定的全局参考电平来写入时，这些单元被重新编程，以设置跟踪和用户单元编程的阈值。每次读取用户单元时，读取跟踪单元的阈值电压，并且这些阈值用于确定用户单元的存储的逻辑电平。在一组实施例中，一个或多个跟踪单元的群体与多状态存储器的不同逻辑电平相关联。这些跟踪单元群可以仅提供逻辑电平的子集。基于该子集，针对所有逻辑电平导出用于转换阈值电压的读取点。在一个实施例中，由多个跟踪单元组成的两个群组与多位单元的两个逻辑电平相关联。在模拟实现中，使用跟踪单元格群体的模拟阈值直接读取用户单元，而不首先将其转换为数字值。一组替代实施例提供使用不同的电压和/或定时来跟踪单元的写入，以便在跟踪单元的最终写入阈值中提供较小的不确定性。

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