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    • 7. 发明授权
    • System and method for achieving fast switching of analog voltages on large capacitive load
    • 在大电容负载下实现模拟电压的快速切换的系统和方法
    • US06486715B2
    • 2002-11-26
    • US09825615
    • 2001-04-02
    • Geoffrey S. GongwerShahzad Khalid
    • Geoffrey S. GongwerShahzad Khalid
    • H03K17687
    • G11C5/145G11C8/08
    • Driver (100) and method are provided for driving capacitive load (120) that achieve an improved response time without increasing power consumption of the driver. Driver (100) has load buffer (105) with an input (110) for receiving an input voltage (VIN), and an output 115 for coupling an output voltage (VOUT) to load 120. VOUT is driven between a first voltage level (V1) and a second voltage level (V2) in response to changes in VIN. Driver (100) also has reserve circuit (125) with capacitor (130), reserve buffer (135), switch (140) for coupling the capacitor to capacitive load (120) and controller (145) for operating the switch. Reserve buffer (135) has an input (150) for receiving an input voltage (VRES—IN), and an output (155) for coupling an output voltage (VRES—OUT) to capacitor (130) to charge the capacitor. Controller (145) is configured to operate switch (140) to couple capacitor (130) to capacitive load (120) when VOUT is being driven between V1 and V2.
    • 驱动器(100)和方法被提供用于驱动电容性负载(120),其实现改善的响应时间,而不增加驱动器的功率消耗。 驱动器(100)具有负载缓冲器(105),其具有用于接收输入电压(VIN)的输入端(110)和用于将输出电压(VOUT)耦合到负载120的输出端115.VOUT在第一电压电平 V1)和响应于VIN变化的第二电压电平(V2)。 驱动器(100)还具有用于将电容器耦合到电容性负载(120)的开关(140)和用于操作开关的控制器(145)的具有电容器(130),保留缓冲器(135)的开关(140)。 保留缓冲器(135)具有用于接收输入电压(VRES-IN)的输入端(150)和用于将输出电压(VRES-OUT)耦合到电容器(130)以对电容器充电的输出端(155)。 当VOUT在V1和V2之间被驱动时,控制器(145)被配置为操作开关(140)以将电容器(130)耦合到电容性负载(120)。
    • 8. 发明授权
    • Smart verify for multi-state memories
    • 智能验证多状态存储器
    • US07243275B2
    • 2007-07-10
    • US11304961
    • 2005-12-14
    • Geoffrey S. GongwerDaniel C. GutermanYupin Kawing Fong
    • Geoffrey S. GongwerDaniel C. GutermanYupin Kawing Fong
    • G11C29/00G11C7/00
    • G11C11/5635G11C11/5628G11C16/3454G11C16/3459G11C2211/5621
    • A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.
    • 提出了一种“智能验证”技术,其中使用基于验证结果的动态调整多状态验证范围对基于顺序状态的验证实现来编程多状态存储器。 该技术可以通过提供“智能”元件来最小化写入序列的每个程序/验证/锁定步骤的顺序验证操作的数量,从而提高多状态写入速度,同时在顺序验证的多状态存储器实现中保持可靠的操作。 在程序/验证周期序列的开始,在验证阶段只检查最低的状态或状态。 当达到较低的状态时,额外的更高的状态被添加到验证序列中,并且可以去除较低的状态。