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1. 发明授权

US07730261B1 Multicore memory management system 失效
标题翻译：多内存管理系统
公开(公告)号：US07730261B1
公开(公告)日：2010-06-01
申请号：US11507880
申请日：2006-08-21
申请人： Geoffrey K. Yung , Chia-Hung Chien
发明人： Geoffrey K. Yung , Chia-Hung Chien
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F12/084 , G06F13/1663 , G06F2212/1016
摘要： A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.
摘要翻译：多处理系统部分地包括各自与总线直接通信的多个处理单元，与总线直接通信的多个存储器单元，以及至少一个不与总线直接通信但不能直接与总线通信的共享存储器多个处理单元。共享存储器可以是存储指令和/或数据的高速缓冲存储器。共享存储器包括多个存储体，其第一子集可以存储数据，并且其第二子集可以存储指令。冲突检测块根据多个地址位和预定义的仲裁方案来解决对每个存储体的访问冲突。冲突检测块在时钟信号的连续周期期间为每个处理单元提供对存储体的顺序访问。

2. 发明授权

US07984246B1 Multicore memory management system 有权
标题翻译：多内存管理系统
公开(公告)号：US07984246B1
公开(公告)日：2011-07-19
申请号：US12755893
申请日：2010-04-07
申请人： Geoffrey K. Yung , Chia-Hung Chien
发明人： Geoffrey K. Yung , Chia-Hung Chien
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F12/084 , G06F13/1663 , G06F2212/1016
摘要： A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.
摘要翻译：多处理系统部分地包括各自与总线直接通信的多个处理单元，与总线直接通信的多个存储器单元，以及至少一个不与总线直接通信但不能直接与总线通信的共享存储器多个处理单元。共享存储器可以是存储指令和/或数据的高速缓冲存储器。共享存储器包括多个存储体，其第一子集可以存储数据，并且其第二子集可以存储指令。冲突检测块根据多个地址位和预定义的仲裁方案来解决对每个存储体的访问冲突。冲突检测块在时钟信号的连续周期期间为每个处理单元提供对存储体的顺序访问。

3. 发明授权

US07949833B1 Transparent level 2 cache controller 有权
标题翻译：透明级2缓存控制器
公开(公告)号：US07949833B1
公开(公告)日：2011-05-24
申请号：US12728583
申请日：2010-03-22
申请人： Hong-Yi Chen , Geoffrey K. Yung
发明人： Hong-Yi Chen , Geoffrey K. Yung
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/0811 , G06F12/0837
摘要： A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.
摘要翻译：连接到采用物理地址的总线的数字系统包括一个处理核心。一级（L1）缓存与处理核心通信。二级（L2）缓存与L1高速缓存通信。 L1高速缓存和L2高速缓存由虚拟地址索引并用虚拟地址标记。总线单元与二级缓存和总线进行通信。

4. 发明授权

US08347034B1 Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access 有权
标题翻译：透明的2级缓存，使用独立的标签和有效的随机存取存储器阵列进行缓存访问
公开(公告)号：US08347034B1
公开(公告)日：2013-01-01
申请号：US11034846
申请日：2005-01-13
申请人： Hong-Yi Chen , Geoffrey K. Yung
发明人： Hong-Yi Chen , Geoffrey K. Yung
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0837
摘要： A computer cache for a memory comprises a data random-access memory (RAM) containing a plurality of cache lines. Each of the cache lines stores a segment of the memory. A tag RAM contains a plurality of address tags that correspond to the cache lines. A valid RAM contains a plurality of validity values that correspond to the cache lines. The valid RAM is stored separately from the tag RAM and the data RAM. The valid RAM is selectively independently clearable. A hit module determines whether data is stored in the computer cache based upon the valid RAM and the tag RAM.
摘要翻译：用于存储器的计算机缓存器包括包含多个高速缓存线的数据随机存取存储器（RAM）。每个高速缓存线存储存储器的一段。标签RAM包含与高速缓存行对应的多个地址标签。有效RAM包含与高速缓存行对应的多个有效值。有效的RAM与标签RAM和数据RAM分开存储。有效的RAM可以选择性地独立清除。命中模块基于有效的RAM和标签RAM来确定数据是否存储在计算机高速缓存中。

5. 发明授权

US07730285B1 Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof 有权
标题翻译：具有部分旁路重排序缓冲器和组合加载/存储算术逻辑单元的数据处理系统及其处理方法
公开(公告)号：US07730285B1
公开(公告)日：2010-06-01
申请号：US11497805
申请日：2006-08-02
申请人： Hong-Yi Chen , Richard Lee , Geoffrey K. Yung , Jensen Tjeng
发明人： Hong-Yi Chen , Richard Lee , Geoffrey K. Yung , Jensen Tjeng
IPC分类号： G06F9/312
CPC分类号： G06F9/3838 , G06F9/3828 , G06F9/3855 , G06F9/3857
摘要： A data processing system includes a plurality of functional units that selectively execute instructions. A register file includes a plurality of registers that store data corresponding to the instructions. A reorder buffer communicates with the register file and stores the data, includes at least one bypassable buffer location, and includes at least one non-bypassable buffer location.
摘要翻译：数据处理系统包括有选择地执行指令的多个功能单元。寄存器文件包括存储对应于指令的数据的多个寄存器。重排序缓冲器与寄存器文件通信并存储数据，包括至少一个可旁路缓冲器位置，并且包括至少一个不可旁路缓冲器位置。

6. 发明授权

US07685372B1 Transparent level 2 cache controller 失效
标题翻译：透明级2缓存控制器
公开(公告)号：US07685372B1
公开(公告)日：2010-03-23
申请号：US11034677
申请日：2005-01-13
申请人： Hong-Yi Chen , Geoffrey K. Yung
发明人： Hong-Yi Chen , Geoffrey K. Yung
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/0811 , G06F12/0837
摘要： A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.
摘要翻译：连接到采用物理地址的总线的数字系统包括一个处理核心。一级（L1）缓存与处理核心通信。二级（L2）缓存与L1高速缓存通信。 L1高速缓存和L2高速缓存由虚拟地址索引并用虚拟地址标记。总线单元与二级缓存和总线进行通信。

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