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1. 发明申请

US20150316723A1 Fiber Optic Coupler Array 有权
标题翻译：光纤耦合器阵列
公开(公告)号：US20150316723A1
公开(公告)日：2015-11-05
申请号：US14104230
申请日：2013-12-12
申请人： Geoff W. Taylor , Yan Zhang
发明人： Geoff W. Taylor , Yan Zhang
IPC分类号： G02B6/30 , G02F1/017 , G02B6/14 , G02B6/122 , G02B6/12
CPC分类号： G02B6/305 , G02B6/1228 , G02B6/14 , G02B6/421 , G02B6/423 , G02B6/4249 , G02B6/4257
摘要： An assembly includes optical fibers each having a waveguide core, a photonic integrated circuit (IC) that includes in-plane waveguides corresponding to the optical fibers, and a substrate bonded to the photonic IC with grooves that support the optical fibers. The substrate and photonic IC can have metal bumps that cooperate to provide mechanical bonding and electrical connections between the substrate and photonic IC. Portions of the optical fibers supported by the substrate grooves can define flat surfaces spaced from the optical fiber cores. The photonic IC can include passive waveguide structures with a first coupling section that interfaces to the flat surface of a corresponding optical fiber (for evanescent coupling of optical signals) and a second coupling section that interfaces to a corresponding in-plane waveguide (for adiabatic spot-size conversion of optical signals).
摘要翻译：一种组件包括各自具有波导芯的光纤，包括对应于光纤的面内波导的光子集成电路（IC）以及与支撑光纤的凹槽连接到光子IC的基板。衬底和光子IC可以具有金属凸块，其配合以在衬底和光子IC之间提供机械结合和电连接。由基板槽支撑的光纤的一部分可以限定与光纤芯间隔开的平坦表面。光子IC可以包括无源波导结构，其具有与对应光纤的平坦表面（用于光信号的渐逝耦合）相接合的第一耦合部分和与对应的平面波导（用于绝热光点）相连接的第二耦合部分光信号的尺寸转换）。

2. 发明申请

US20220059993A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHODOLOGY FOR MAKING SAME 有权
公开(公告)号：US20220059993A1
公开(公告)日：2022-02-24
申请号：US17408424
申请日：2021-08-21
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01S5/20 , H01S5/183 , H01S5/062 , H01S5/042
摘要： Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

3. 发明授权

US07409120B2 Integrated circuit for programmable optical delay 有权
标题翻译：用于可编程光延迟的集成电路
公开(公告)号：US07409120B2
公开(公告)日：2008-08-05
申请号：US11424012
申请日：2006-06-14
申请人： Geoff W. Taylor , Jianhong Cai , Daniel C. Upp
发明人： Geoff W. Taylor , Jianhong Cai , Daniel C. Upp
IPC分类号： G02B6/12
CPC分类号： H01Q1/525 , H03M3/43 , H03M3/454 , H03M3/456 , H04B1/525
摘要： Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.
摘要翻译：通过改进的信号消除系统有效地消除由从发射天线发射到接收天线的发射信号的传播引起的干扰。该系统包括产生所述发射信号的时间延迟和幅度减小的表示的干扰消除信号发生器。求和级可操作地耦合到干扰消除信号发生器和接收天线。求和级从接收信号中减去发射信号的时间延迟和幅度减小的表示，以基本上消除干扰。干扰消除信号发生器优选地包括一种新颖的可编程光学延迟线，其将可变量的光学延迟引入到从所述发射信号导出的光学信号，以及基于可控硅的Σ-Δ调制器，其将发射信号的采样转换为光域中的数字信号。

4. 发明授权

US07064697B2 Photonic sigma delta analog-to-digital conversation employing dual heterojunction thyristors 有权
标题翻译：采用双异质结晶闸管的光子Σ-Δ模数转换对话
公开(公告)号：US07064697B2
公开(公告)日：2006-06-20
申请号：US10602217
申请日：2003-06-24
申请人： Geoff W. Taylor , Jianhong Cai , Daniel C. Upp
发明人： Geoff W. Taylor , Jianhong Cai , Daniel C. Upp
IPC分类号： H03M1/00
CPC分类号： H01Q1/525 , H03M3/43 , H03M3/454 , H03M3/456 , H04B1/525
摘要： Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.
摘要翻译：通过改进的信号消除系统有效地消除由从发射天线发射到接收天线的发射信号的传播引起的干扰。该系统包括产生所述发射信号的时间延迟和幅度减小的表示的干扰消除信号发生器。求和级可操作地耦合到干扰消除信号发生器和接收天线。求和级从接收信号中减去发射信号的时间延迟和幅度减小的表示，以基本上消除干扰。干扰消除信号发生器优选地包括一种新颖的可编程光学延迟线，其将可变量的光学延迟引入到从所述发射信号导出的光学信号，以及基于可控硅的Σ-Δ调制器，其将发射信号的采样转换为光域中的数字信号。

5. 发明授权

US07012274B2 Modulation doped thyristor and complementary transistors combination for a monolithic optoelectronic integrated circuit 有权
标题翻译：用于单片光电集成电路的调制掺杂晶闸管和互补晶体管组合
公开(公告)号：US07012274B2
公开(公告)日：2006-03-14
申请号：US10469649
申请日：2002-03-04
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01L29/06
CPC分类号： B82Y20/00 , G02B6/28 , G02B6/2821 , G02F1/025 , H01L27/0605 , H01L29/165 , H01L29/205 , H01L29/66227 , H01L29/7371 , H01L29/74 , H01L29/7783 , H01L31/035236 , H01L31/10 , H01L31/1113
摘要： A thyristor and family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate (149) with an epitaxial layer structure comprised of two modulation doped transistor structures inverted with respect to each other. The transistor structures are obtained by adding planar doping to the Pseudomorphic High Electron Mobility Transistor (PHEMT) structure. For one transistor, two sheets of planar doping of the same polarity separated by a lightly doped layer are added which are opposite to the modulation doping of the PHEMT. The combination is separated from the PHEMT modulation doping by undoped material. The charge sheets are thin and highly doped. The top charge sheet (168) achieves low gate contact resistance and the bottom charge sheet (153) defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT For the other transistor, only one additional sheet is added.
摘要翻译：在具有由相对于彼此反转的两个调制掺杂晶体管结构的外延层结构的单片基板（149）上获得晶闸管和高速晶体管和光电子器件系列。通过向Pseudomorphic高电子迁移率晶体管（PHEMT）结构添加平面掺杂获得晶体管结构。对于一个晶体管，添加由轻掺杂层分开的相同极性的两片平面掺杂，其与PHEMT的调制掺杂相反。该组合与未掺杂材料的PHEMT调制掺杂分离。充电片薄且高度掺杂。顶部充电片（168）实现了低栅极接触电阻，并且底部充电片（153）相对于PHEMT的调制掺杂层限定了场效应晶体管（FET）的电容。对于另一个晶体管，仅一个附加工作表被添加。

6. 发明授权

US06936839B2 Monolithic integrated circuit including a waveguide and quantum well inversion channel devices and a method of fabricating same 有权
标题翻译：包括波导和量子阱反转通道器件的单片集成电路及其制造方法
公开(公告)号：US06936839B2
公开(公告)日：2005-08-30
申请号：US10292127
申请日：2002-11-12
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01L29/20 , H01L29/778 , H01S5/026 , H01S5/183 , H01S5/323 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01S5/18308 , G02F1/01708 , H01L29/2003 , H01L29/7785 , H01S5/06203 , H01S5/32341 , H01S5/32366
摘要： A family of optical waveguide structures and high speed optoelectronic/transistor devices are obtained from a multilayer structure that includes a modulation doped quantum well structure formed over a DBR mirror. The optical waveguide structure is realized by implanting n-type ions to form a pair of n-type implant regions that define a waveguide region therebetween. An oxide layer (e.g., SiO2) is deposited over the waveguide region. A thermal annealing operation causes the oxide layer to introduce impurity free vacancy disordering that substantially eliminates absorption in the waveguide region. The waveguide region contributes to lateral confinement of light therein. An etching operation etches through the n-type implant regions to define sidewalls, which are subject to an oxidation operation that produces oxidized sections along the sidewalls. The oxide layer is removed, and a top distributed bragg reflector mirror is formed over the waveguide region. The resulting structure realizes an optical waveguide. Optoelectronic devices (including lasers, detectors, modulators, amplifiers) and transistor devices (including enhancement-mode and depletion mode JFET devices and bipolar-type devices) are also realized from the same multi-layer structure and share many of the fabrication steps of the optical waveguide, to thereby provide for efficient monolithic integration of a broad array of optical/optoelectronic/electronic devices.
摘要翻译：从包括在DBR镜上形成的调制掺杂量子阱结构的多层结构获得一系列光波导结构和高速光电子/晶体管器件。光波导结构通过注入n型离子形成一对在其间形成波导区域的n型注入区实现。氧化物层（例如，SiO 2）沉积在波导区域上。热退火操作导致氧化物层引入无杂质的空位无序，其基本上消除了波导区域中的吸收。波导区域有助于其中的光的侧向限制。蚀刻操作蚀刻穿过n型注入区域以限定侧壁，其经受沿着侧壁产生氧化部分的氧化操作。去除氧化物层，并且在波导区域上形成顶部分布式布拉格反射镜。所得到的结构实现了光波导。光电子器件（包括激光器，检测器，调制器，放大器）和晶体管器件（包括增强型和耗尽型JFET器件和双极型器件）也通过相同的多层结构实现，并且共享许多制造步骤光波导，从而提供广泛的光/光电子/电子器件阵列的有效单片集成。

7. 发明授权

US06841806B1 Heterojunction thyristor-based amplifier 失效
标题翻译：基于异质结晶闸管的放大器
公开(公告)号：US06841806B1
公开(公告)日：2005-01-11
申请号：US10602218
申请日：2003-06-24
申请人： Geoff W. Taylor , Jianhong Cai
发明人： Geoff W. Taylor , Jianhong Cai
IPC分类号： H01L27/08 , H01L29/15 , H01L29/74 , H01L31/111 , H01L31/0328
CPC分类号： H01L29/74 , H01L27/0817 , H01L29/155 , H01L31/1113
摘要： An integrated circuit includes a heterojunction thyristor device having an anode terminal, a cathode terminal, a first injector terminal operably coupled to a first quantum well channel disposed between the anode terminal and the cathode terminal, and a second injector terminal operably coupled to a second quantum well channel disposed between the anode terminal and the cathode terminal. Bias elements operate the heterojunction thyristor device in a mode that provides substantially linear voltage gain for electrical signals supplied to at least one of the first and second injector terminals for output to at least one output node. Preferably, the bias elements include a first DC current source operably coupled to an n-type modulation doped quantum well structure, a second DC current source operably coupled to a p-type modulation doped quantum well structure, a first bias resistance operably coupled between a high voltage supply and the anode terminal, and a second bias resistance operably coupled between the cathode terminal and a low voltage supply. The bias elements provide a current passing from the anode terminal to the cathode terminal that is below a characteristic hold current for the heterojunction thyristor device to thereby inhibit switching of the heterojunction thyristor device. The DC current provided by the DC current sources controls the amount of voltage gain provided by the heterojunction thyristor device.
摘要翻译：集成电路包括具有阳极端子，阴极端子，可操作地耦合到设置在阳极端子和阴极端子之间的第一量子阱沟道的第一注入端子的异质结晶闸管器件和可操作地耦合到第二量子阱的第二注入器端子阱通道设置在阳极端子和阴极端子之间。偏置元件以对提供给第一和第二注入器端子中的至少一个的电信号提供基本上线性的电压增益以输出到至少一个输出节点的模式来操作异质结晶闸管器件。优选地，偏置元件包括可操作地耦合到n型调制掺杂量子阱结构的第一DC电流源，可操作地耦合到p型调制掺杂量子阱结构的第二DC电流源，可操作地耦合在高电压电源和阳极端子，以及可操作地耦合在阴极端子和低电压电源之间的第二偏置电阻。偏置元件提供从阳极端子到阴极端子的电流，该电流低于异质结晶闸管器件的特性保持电流，从而阻止异质结晶闸管器件的切换。由直流电流源提供的直流电流控制由异质结晶闸管器件提供的电压增益的量。

8. 发明授权

US06841795B2 Semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation 有权
标题翻译：采用至少一个调制掺杂量子阱结构和一个或多个蚀刻停止层的半导体器件用于精确的接触形成
公开(公告)号：US06841795B2
公开(公告)日：2005-01-11
申请号：US10340942
申请日：2003-01-13
申请人： Geoff W. Taylor , Scott W. Duncan
发明人： Geoff W. Taylor , Scott W. Duncan
IPC分类号： H01L21/331 , H01L21/335 , H01L29/15 , H01L29/737 , H01L29/80 , H03K17/79 , H03M1/66 , H03M1/74 , H03M1/80
CPC分类号： H01L29/66318 , H01L29/155 , H01L29/66462 , H01L29/7371 , H01L29/802 , H03K17/79 , H03M1/667 , H03M1/74 , H03M1/808
摘要： A semiconductor device includes a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used to form contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well structure. Thin capping layers are also provided to protect certain layers from oxidation. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).In another aspect of the present invention, a high performance bipolar transistor device is realized from this structure by implanting p-type ions in a interdigitization pattern that forms a plurality of p-type ion implant regions on both sides of the p-type modulation doped quantum well structure to a depth that penetrates the n-type ohmic contact layer. The interdigitization pattern of the p-type implants reduces capacitance between the p-type modulation doped quantum well structure and the n-type ohmic contact layer to enable higher frequency operation.
摘要翻译：半导体器件包括在衬底上形成的一系列层，所述层包括包括n型欧姆接触层，p型调制掺杂量子阱结构，n型调制掺杂量子阱结构的第一多个层，以及包括p型欧姆接触层的第四多个层。蚀刻停止层用于形成与n型欧姆接触层的接触并与n型调制掺杂量子阱结构接触。还提供薄盖层以保护某些层免于氧化。优选地，每个这样的蚀刻停止层被制成足够薄以允许在从该结构实现的光电子/电子器件的操作期间电流隧穿（包括异质结晶闸管器件，n沟道HFET器件，p沟道HFET器件，p型量子阱器件，基极双极型晶体管器件和n型量子阱基双极型晶体管器件）。在本发明的另一方面，通过将p型离子注入叉指形式中，从该结构实现了高性能双极晶体管器件其在p型调制掺杂量子阱结构的两侧上形成穿过n型欧姆接触层的深度的多个p型离子注入区域。 p型植入物的叉指形式降低p型调制掺杂量子阱结构和n型欧姆接触层之间的电容，以实现更高频率的操作。

9. 发明授权

US6031243A Grating coupled vertical cavity optoelectronic devices 失效
标题翻译：光栅耦合垂直腔光电器件
公开(公告)号：US6031243A
公开(公告)日：2000-02-29
申请号：US949502
申请日：1997-10-14
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01S5/062 , H01S5/183 , H01L29/06 , H01L33/00 , H01S5/32
CPC分类号： H01S5/2027 , H01S5/18372 , H01S5/2275 , H01S5/0424 , H01S5/06203 , H01S5/06226 , H01S5/12 , H01S5/18308 , H01S5/18341 , H01S5/18369
摘要： A edge emitting waveguide laser is obtained that derives its optical power from a vertical cavity laser structure. The vertical cavity laser with top and bottom Distributed Bragg Reflectors produces stimulated emission by resonance in the vertical direction but the optical power so generated is diffracted by a second order grating into an optical mode propagating in the optical waveguide formed by the upper and lower mirrors as cladding layers. The efficiency of the diffraction grating and the reflectivity of the mirrors are maximized so that essentially all of the light is coupled into the guide and the loss through the mirrors can be neglected. The same structure can be utilized as a detector, a modulator or an amplifier. The designated laser structure to achieve this form of operation is the inversion channel laser which is a laterally injected laser having both contacts on the top side of the device. Then the anode and cathode of the laser are essentially coplanar electrodes and the device is implemented in the form of a traveling wave laser, detector, modulator or amplifier which forms the basis for very high frequency performance.
摘要翻译：获得从垂直腔激光器结构导出其光功率的边缘发射波导激光器。具有顶部和底部分布布拉格反射器的垂直腔激光器在垂直方向上通过谐振产生受激发射，但是所产生的光功率由第二级光栅衍射成在由上镜和下反射镜形成的光波导中传播的光模，如包层衍射光栅的效率和反射镜的反射率最大化，使得基本上所有的光被耦合到引导件中，并且可以忽略通过反射镜的损耗。相同的结构可以用作检测器，调制器或放大器。实现这种形式的操作的指定的激光结构是反转通道激光器，其是在器件的顶侧上具有两个触点的横向注入的激光器。然后激光器的阳极和阴极基本上是共面电极，并且器件以行波激光器，检测器，调制器或放大器的形式实现，其形成非常高频率性能的基础。

10. 发明授权

US07556976B2 Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation 有权
标题翻译：使用至少一个调制掺杂量子阱结构和一个或多个蚀刻停止层来制造半导体器件以准确接触形成的方法
公开(公告)号：US07556976B2
公开(公告)日：2009-07-07
申请号：US11360756
申请日：2006-02-23
申请人： Geoff W. Taylor , Scott W. Duncan
发明人： Geoff W. Taylor , Scott W. Duncan
IPC分类号： H01L21/00
CPC分类号： H01L29/155 , H01L21/8252 , H01L27/0605 , H01L29/0646 , H01L29/0653 , H01L29/0821 , H01L29/0843 , H01L29/1004 , H01L29/1066 , H01L29/1075 , H01L29/66318 , H01L29/7371 , H01L29/74 , H01L29/7783 , H03K17/79 , H03M1/667 , H03M1/74 , H03M1/808
摘要： A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used during etching operations when forming contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices). The etch stop layer(s) preferably comprise AlAs that functions as an etch stop during etching by a chlorine-based gas mixture that includes fluorine. The series of layers preferably comprise group III-V materials.
摘要翻译：制造半导体器件的方法包括以下步骤：形成（或提供）在衬底上形成的一系列层，所述层包括包括n型欧姆接触层，p型调制掺杂量子阱的第一多个层结构，n型调制掺杂量子阱结构，以及包括p型欧姆接触层的第四多层。当与n型欧姆接触层形成接触并与n型调制掺杂量子阱接触时，在蚀刻操作期间使用蚀刻停止层。优选地，每个这样的蚀刻停止层被制成足够薄以允许在从该结构实现的光电子/电子器件的操作期间电流隧穿（包括异质结晶闸管器件，n沟道HFET器件，p沟道HFET器件，p型量子阱器件，基极双极晶体管器件和n型量子阱基双极晶体管器件）。蚀刻停止层优选地包括在通过包括氟的氯基气体混合物蚀刻期间用作蚀刻停止的AlAs。该系列层优选包含III-V族材料。

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