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1. 发明授权

US06212664B1 Method and system for estimating an input data sequence based on an output data sequence and hard disk drive incorporating same 失效
标题翻译：用于基于输出数据序列和包含其的硬盘驱动器来估计输入数据序列的方法和系统
公开(公告)号：US06212664B1
公开(公告)日：2001-04-03
申请号：US09060918
申请日：1998-04-15
申请人： Gennady Feygin , Robert B. Staszewski , Michel Combes
发明人： Gennady Feygin , Robert B. Staszewski , Michel Combes
IPC分类号： H03M1303
CPC分类号： H03M13/39
摘要： A method for generating an updated path metric includes combining each of first and second provisional path metric first portions with an associated branch metric first portion to produce a first provisional updated path metric first portion candidate and a second provisional updated path metric first portion candidate, respectively. The method also includes selecting one of the provisional first portion updated path metric candidates to produce an updated path metric first portion candidate and combining any carry component of the selected updated path metric first portion candidate with a path metric second portion and a branch metric second portion to produce a first updated path metric second portion candidate. The method also includes comparing the updated path metric second portion candidate to at least one other updated path metric second portion candidate; and selecting one of the updated path metric second portion candidates to produce an updated path metric second portion.
摘要翻译：用于生成更新的路径量度的方法包括将第一和第二临时路径度量第一部分中的每一个与相关联的分支度量第一部分组合以分别产生第一临时更新路径度量第一部分候选和第二临时更新路径量度第一部分候选。该方法还包括选择临时第一部分更新路径度量候选之一以产生更新的路径量度第一部分候选，并将所选择的更新路径度量第一部分候选的任何进位分量与路径度量第二部分和分支度量第二部分以产生第一更新路径度量第二部分候选。该方法还包括将更新的路径度量第二部分候选与至少一个其他更新路径度量第二部分候选进行比较; 以及选择更新的路径度量第二部分候选中的一个，以产生更新的路径量度第二部分。

2. 发明授权

US07983375B2 Variable delay oscillator buffer 有权
标题翻译：可变延迟振荡器缓冲器
公开(公告)号：US07983375B2
公开(公告)日：2011-07-19
申请号：US12021205
申请日：2008-01-28
申请人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
发明人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
IPC分类号： H03D3/24
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.
摘要翻译：一种新颖有用的可变延迟数字控制晶体振荡器（DCXO）缓冲器（即切片器）。在DCXO之后的常规限幅器被修改以将受控的随机可变延迟引入缓冲的DCXO时钟。结果输出时钟信号然后被用作ADPLL电路的TDC的输入，以减轻由通过晶体管的LO / TX耦合引起的次谐波混合的劣化，并且减轻由于有限分辨率引起的死区效应 TDC。介绍了将可变延迟引入到缓冲DCXO输出时钟信号中的两种机制：第一种在精细步骤中产生可变延迟的机制，以及在粗略步骤中产生可变延迟的第二种机制。在这两种机制中，开关被合并到限幅器电路中，并使用可包括抖动信号的数字位序列进行控制。开关通过改变切片器时钟输出的延迟的数字位序列被导通和关断，其用于移位所产生的输出时钟信号的上升和下降转换点。抖动被转移到较高的频率，由PLL环路滤波器滤波。

3. 发明授权

US07647192B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07647192B2
公开(公告)日：2010-01-12
申请号：US10924297
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

4. 发明授权

US07466777B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07466777B2
公开(公告)日：2008-12-16
申请号：US10924159
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

5. 发明授权

US07466207B2 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US07466207B2
公开(公告)日：2008-12-16
申请号：US11619529
申请日：2007-01-03
申请人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
发明人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
IPC分类号： H03C3/06 , H03L7/091 , H03L7/099
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

6. 发明授权

US07103489B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US07103489B2
公开(公告)日：2006-09-05
申请号：US10924303
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

7. 发明授权

US07183860B2 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US07183860B2
公开(公告)日：2007-02-27
申请号：US11149859
申请日：2005-06-10
申请人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
发明人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
IPC分类号： H03C3/06 , H03L7/091 , H03L7/099
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

8. 发明授权

US06856925B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US06856925B2
公开(公告)日：2005-02-15
申请号：US10269349
申请日：2002-10-11
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： H03D7/12 , H04B1/10 , G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

9. 发明申请

US20080192876A1 VARIABLE DELAY OSCILLATOR BUFFER 有权
标题翻译：可变延迟振荡器缓冲器
公开(公告)号：US20080192876A1
公开(公告)日：2008-08-14
申请号：US12021205
申请日：2008-01-28
申请人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
发明人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
IPC分类号： H03D3/24
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.
摘要翻译：一种新颖有用的可变延迟数字控制晶体振荡器（DCXO）缓冲器（即切片器）。在DCXO之后的常规限幅器被修改以将受控的随机可变延迟引入缓冲的DCXO时钟。结果输出时钟信号然后被用作ADPLL电路的TDC的输入，以减轻由通过晶体管的LO / TX耦合引起的次谐波混合的劣化，并且减轻由于有限分辨率引起的死区效应 TDC。介绍了将可变延迟引入到缓冲DCXO输出时钟信号中的两种机制：第一种在精细步骤中产生可变延迟的机制，以及在粗略步骤中产生可变延迟的第二种机制。在这两种机制中，开关被合并到限幅器电路中，并使用可包括抖动信号的数字位序列进行控制。开关通过改变切片器时钟输出的延迟的数字位序列被导通和关断，其用于移位所产生的输出时钟信号的上升和下降转换点。抖动被转移到较高的频率，由PLL环路滤波器滤波。

10. 发明授权

US6037886A Method and apparatus for extracting band and error values from digital samples of an analog signal 失效
标题翻译：用于从模拟信号的数字样本中提取频带和误差值的方法和装置
公开(公告)号：US6037886A
公开(公告)日：2000-03-14
申请号：US53867
申请日：1998-04-01
申请人： Robert B. Staszewski , Gennady Feygin
发明人： Robert B. Staszewski , Gennady Feygin
IPC分类号： G11B20/10 , H03M1/06 , H03M1/18 , H03M1/62
CPC分类号： H03M1/0624 , G11B20/10009 , G11B20/10055 , H03M1/185
摘要： A read channel circuit (27) for a hard disk drive system (10) includes an analog-to-digital converter (38) having an output (39) which is supplied through a filter (41) to a detector (46) and to a band/error circuit (47). The band/error circuit extracts from the filter output a band value (48) and an error value (49). The band and error values are used by a timing recovery loop (51, 53) to control the operation of the analog-to-digital converter, and are used by a gain recovery loop (51, 54) to facilitate an automatic gain control function for an analog circuit (36). The band/error circuit uses targets and thresholds which are each a power of two, so that a predetermined number of the least significant bits from the output of the filter can be used as the error value, without modification. The band value is determined from the most significant bits of the output of the filter. The filter not only shapes the signal spectrum, but also performs an integer space transformation that normalizes the output of the analog-to-digital converter with respect to the predetermined targets and thresholds of the band/error circuit.
摘要翻译：用于硬盘驱动系统（10）的读通道电路（27）包括具有通过滤波器（41）提供给检测器（46）的输出（39）的模拟 - 数字转换器（38），并且频带/误差电路（47）。频带/误差电路从滤波器输出提取频带值（48）和误差值（49）。频带和误差值由定时恢复环路（51,53）用于控制模数转换器的操作，并且由增益恢复回路（51,54）使用以便于自动增益控制功能用于模拟电路（36）。频带/误差电路使用各自为2的幂的目标和阈值，使得可以将来自滤波器的输出的预定数量的最低有效位用作误差值，而无需修改。从滤波器输出的最高有效位确定频带值。滤波器不仅对信号频谱进行整形，而且还执行整数空间变换，其相对于预定目标和频带/误差电路的阈值对模数转换器的输出进行归一化。

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