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1. 发明申请

US20060002165A1 High speed memory modules utilizing on-trace capacitors 有权
公开(公告)号：US20060002165A1
公开(公告)日：2006-01-05
申请号：US10882459
申请日：2004-06-30
申请人： Ge Chang , Hany Fahmy
发明人： Ge Chang , Hany Fahmy
IPC分类号： G11C5/06
CPC分类号： G06F13/4086
摘要： Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.

2. 发明申请

US20150279444A1 APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：用于提供集成电路封装多个引脚的终止的装置，方法和系统
公开(公告)号：US20150279444A1
公开(公告)日：2015-10-01
申请号：US14440068
申请日：2013-11-22
申请人： George VERGIS , Kuljit S. BAINS , James A. MCCALL , Ge CHANG , INTEL CORPORATION
发明人： George Vergis , Kuljit S. Bains , James A. McCall , Ge Chang
IPC分类号： G11C11/4074 , G11C7/10 , G06F13/16 , G11C11/408
CPC分类号： G11C11/4074 , G06F3/0604 , G06F3/0637 , G06F3/0673 , G06F13/1663 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C7/109 , G11C8/06 , G11C11/408 , Y10T29/41
摘要： Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series
摘要翻译：用于为存储器件的多个芯片提供终端的技术和机制。在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

3. 发明授权

US07151683B2 High speed memory modules utilizing on-trace capacitors 有权
标题翻译：高速存储器模块，利用标示电容
公开(公告)号：US07151683B2
公开(公告)日：2006-12-19
申请号：US10882459
申请日：2004-06-30
申请人： Ge Chang , Hany M. Fahmy
发明人： Ge Chang , Hany M. Fahmy
IPC分类号： G11C5/06
CPC分类号： G06F13/4086
摘要： Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.
摘要翻译：用于产生具有连接到存储器总线的多个动态随机存取存储器（DRAM）器件或同步随机存取存储器（SDRAM）器件）的存储器模块的装置和方法，每个DRAM或SDRAM器件经由传输信号（TS ）行。存储器总线包括至少一条TS线，其具有与多个DRAM或SDRAM器件并行连接到TS线的电容器，TS线连接到信号插入端和TS线的附接点之间的存储器总线第一个DRAM或SDRAM设备。还讨论了实现存储器模块的计算系统。

4. 发明申请

US20060001443A1 High speed memory modules utilizing on-pin capacitors 有权
标题翻译：高速内存模块采用片上电容
公开(公告)号：US20060001443A1
公开(公告)日：2006-01-05
申请号：US10882626
申请日：2004-06-30
申请人： Brian Wang , Ge Chang
发明人： Brian Wang , Ge Chang
IPC分类号： H03K19/003
CPC分类号： G11C5/04 , G06F13/4086
摘要： Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.
摘要翻译：用于产生具有连接到存储器总线的多个分支的存储器模块的装置和方法，每个分支包含经由至少一个传输信号（TS）线连接到存储器总线的至少一个动态随机存取存储器（DRAM）装置或SDRAM装置和/或至少一个子传输信号（STS）线。存储器模块包括至少一个分支，其包含与TS线或STS线以及DRAM器件或SDRAM器件并联连接的电容器。还讨论了实现存储器模块的计算系统。

5. 发明授权

US07336098B2 High speed memory modules utilizing on-pin capacitors 有权
标题翻译：高速内存模块采用片上电容
公开(公告)号：US07336098B2
公开(公告)日：2008-02-26
申请号：US10882626
申请日：2004-06-30
申请人： Brian Bai-Kuan Wang , Ge Chang
发明人： Brian Bai-Kuan Wang , Ge Chang
IPC分类号： H03K19/177 , G11C5/06
CPC分类号： G11C5/04 , G06F13/4086
摘要： Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.
摘要翻译：用于产生具有连接到存储器总线的多个分支的存储器模块的装置和方法，每个分支包含经由至少一个传输信号（TS）线连接到存储器总线的至少一个动态随机存取存储器（DRAM）装置或SDRAM装置和/或至少一个子传输信号（STS）线。存储器模块包括至少一个分支，其包含与TS线或STS线以及DRAM器件或SDRAM器件并联连接的电容器。还讨论了实现存储器模块的计算系统。

6. 发明申请

US20050289284A1 High speed memory modules 审中-公开
标题翻译：高速内存模块
公开(公告)号：US20050289284A1
公开(公告)日：2005-12-29
申请号：US10877588
申请日：2004-06-24
申请人： Ge Chang
发明人： Ge Chang
IPC分类号： G06F12/00 , G06F13/40
CPC分类号： G06F13/4086
摘要： Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or synchronous random access memory (SDRAM) device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a resistor connected to the TS line or STS line and connected series with the DRAM device or SDRAM device and connected to the memory bus. A computing system implementing the memory modules is also discussed.
摘要翻译：用于产生具有连接到存储器总线的多个分支的存储器模块的装置和方法，每个分支包含至少一个动态随机存取存储器（DRAM）装置或同步随机存取存储器（SDRAM）装置，其经由至少一个传输信号（TS）线和/或至少一个子传输信号（STS）线。存储器模块包括至少一个分支，其包含连接到TS线或STS线的电阻器，并与DRAM器件或SDRAM器件连接并连接到存储器总线。还讨论了实现存储器模块的计算系统。

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