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1. 发明授权

US07151683B2 High speed memory modules utilizing on-trace capacitors 有权
标题翻译：高速存储器模块，利用标示电容
公开(公告)号：US07151683B2
公开(公告)日：2006-12-19
申请号：US10882459
申请日：2004-06-30
申请人： Ge Chang , Hany M. Fahmy
发明人： Ge Chang , Hany M. Fahmy
IPC分类号： G11C5/06
CPC分类号： G06F13/4086
摘要： Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.
摘要翻译：用于产生具有连接到存储器总线的多个动态随机存取存储器（DRAM）器件或同步随机存取存储器（SDRAM）器件）的存储器模块的装置和方法，每个DRAM或SDRAM器件经由传输信号（TS ）行。存储器总线包括至少一条TS线，其具有与多个DRAM或SDRAM器件并行连接到TS线的电容器，TS线连接到信号插入端和TS线的附接点之间的存储器总线第一个DRAM或SDRAM设备。还讨论了实现存储器模块的计算系统。

2. 发明授权

US07010629B1 Apparatus and method for coupling to a memory module 失效
标题翻译：用于耦合到存储器模块的装置和方法
公开(公告)号：US07010629B1
公开(公告)日：2006-03-07
申请号：US09470542
申请日：1999-12-22
申请人： David W. Frame , Christopher J. Banyai , Karl H. Mauritz , Albert R. Nelson , Quing-Lun Chen , Hany M. Fahmy
发明人： David W. Frame , Christopher J. Banyai , Karl H. Mauritz , Albert R. Nelson , Quing-Lun Chen , Hany M. Fahmy
IPC分类号： G06F13/00
CPC分类号： G06F13/4086 , H01R13/6464 , H01R13/6477
摘要： Briefly, in accordance with one embodiment of the invention, a system includes two boards coupled by a bus. The bus having a dual-terminated transmission line that communicatively couples a memory control hub with a memory repeater hub that each have a Rambus ASIC Cell (RAC). Briefly, in accordance with another embodiment of the invention, a connector has two metal traces that are of different lengths. The parasitic capacitance of the longer metal trace is increased so that the impedance of the two metal traces is substantially equal.
摘要翻译：简而言之，根据本发明的一个实施例，系统包括通过总线耦合的两个板。总线具有双端接传输线，其将存储器控制集线器与每个具有Rambus ASIC单元（RAC）的存储器中继器集线器通信地耦合。简而言之，根据本发明的另一个实施例，连接器具有不同长度的两个金属迹线。较长金属迹线的寄生电容增加，使得两个金属迹线的阻抗基本相等。

3. 发明授权

US07106610B2 High speed memory interface 有权
标题翻译：高速存储器接口
公开(公告)号：US07106610B2
公开(公告)日：2006-09-12
申请号：US10676533
申请日：2003-09-30
申请人： Hany M. Fahmy , Woong H. Ryu
发明人： Hany M. Fahmy , Woong H. Ryu
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G06F13/4086 , H05K1/165
摘要： A memory interface and a method to interface with high-speed memory devices have been disclosed. One embodiment of the memory interface includes an inductor and a number of transmission lines. The transmission lines are coupled to the inductor in series to couple a number of memory devices to a circuit board.
摘要翻译：已经公开了一种存储器接口和与高速存储器件接口的方法。存储器接口的一个实施例包括电感器和多个传输线。传输线串联耦合到电感器，以将多个存储器件耦合到电路板。

4. 发明授权

US06822526B2 Voltage plane with high impedance link 失效
标题翻译：高阻抗链路的电压平面
公开(公告)号：US06822526B2
公开(公告)日：2004-11-23
申请号：US10334961
申请日：2002-12-30
申请人： Woong H. Ryu , Hany M. Fahmy
发明人： Woong H. Ryu , Hany M. Fahmy
IPC分类号： H01P500
CPC分类号： H05K1/0216 , H05K1/0224 , H05K1/0231 , H05K1/165 , H05K2201/09236 , H05K2201/09263 , H05K2201/093 , H05K2201/09663
摘要： According to some embodiments, a voltage plane with a high impedance link is provided. For example, the high impedance link might be a meandered conducting neck between a first low impedance voltage plane portion and a second low impedance voltage plane portion. As other examples, the high impedance link might be a stepped impedance filter or a slotted around filter.
摘要翻译：根据一些实施例，提供具有高阻抗链路的电压平面。例如，高阻抗链路可以是在第一低阻抗电压平面部分和第二低阻抗电压平面部分之间的曲折的导电颈部。作为其他示例，高阻抗链路可以是阶梯式阻抗滤波器或在滤波器周围开槽。

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