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1. 发明授权

US07402846B2 Electrostatic discharge (ESD) protection structure and a circuit using the same 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US07402846B2
公开(公告)日：2008-07-22
申请号：US11254387
申请日：2005-10-20
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H01L27/10 , H01L29/739 , H01L29/73 , H01L29/74 , H01L23/62 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

2. 发明授权

US07348256B2 Methods of forming reduced electric field DMOS using self-aligned trench isolation 有权
标题翻译：使用自对准沟槽隔离形成还原电场DMOS的方法
公开(公告)号：US07348256B2
公开(公告)日：2008-03-25
申请号：US11188921
申请日：2005-07-25
申请人： Gayle W. Miller, Jr. , Volker Dudek , Michael Graf
发明人： Gayle W. Miller, Jr. , Volker Dudek , Michael Graf
IPC分类号： H01L21/76
CPC分类号： H01L29/7824 , H01L21/823481 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/42368 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.
摘要翻译：一种制造电子装置的方法和所得到的电子装置。该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。然后在第一二氧化硅层上形成第一氮化硅层，接着形成第二二氧化硅层。通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。蚀刻的沟槽用另一介质层（例如二氧化硅）填充并平坦化。去除每个前述电介质层，留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。侧壁区域的形成确保全场氧化物厚度，从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。

3. 发明授权

US07848070B2 Electrostatic discharge (ESD) protection structure and a circuit using the same 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US07848070B2
公开(公告)日：2010-12-07
申请号：US12177061
申请日：2008-07-21
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

4. 发明申请

US20080278874A1 ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE AND A CIRCUIT USING THE SAME 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US20080278874A1
公开(公告)日：2008-11-13
申请号：US12177061
申请日：2008-07-21
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, JR. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, JR. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H01L27/06 , H02H9/04
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

5. 发明授权

US07230342B2 Registration mark within an overlap of dopant regions 有权
公开(公告)号：US07230342B2
公开(公告)日：2007-06-12
申请号：US11217250
申请日：2005-08-31
申请人： Franz Dietz , Volker Dudek , Michael Graf , Stefan Schwantes , Gayle W. Miller, Jr.
发明人： Franz Dietz , Volker Dudek , Michael Graf , Stefan Schwantes , Gayle W. Miller, Jr.
IPC分类号： H01L23/544
CPC分类号： G03F7/70425 , G03F7/70633 , G03F9/7076
摘要： A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

6. 发明申请

US20110260250A1 Method And Manufacturing Low Leakage Mosfets And FinFets 有权
标题翻译：方法和制造低漏磁和FinFets
公开(公告)号：US20110260250A1
公开(公告)日：2011-10-27
申请号：US13174398
申请日：2011-06-30
申请人： Gayle W. Miller , Volker Dudek , Michael Graf
发明人： Gayle W. Miller , Volker Dudek , Michael Graf
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.
摘要翻译：通过将晶片的主平面与（100）平面而不是（110）平面对准，可以沿着（100）平面流动的初级电流形成器件。在这种情况下，设备将以大约54.7度与（111）平面相交。这个相交角度可以显着地减少沿（111）方向的应力传播/释放，从而减少缺陷以及泄漏和寄生电流。泄漏电流降低是短路源极 - 漏极结所需的位错长度变化的直接后果。通过使用这种技术，对于N沟道CMOS器件，泄漏电流降低高达两个数量级。

7. 发明申请

US20070262376A1 High-voltage field-effect transistor and method for manufacturing a high-voltage field-effect transistor 失效
标题翻译：高压场效应晶体管及制造高电压场效应晶体管的方法
公开(公告)号：US20070262376A1
公开(公告)日：2007-11-15
申请号：US11518449
申请日：2006-09-11
申请人： Volker Dudek , Michael Graf , Stefan Schwantes
发明人： Volker Dudek , Michael Graf , Stefan Schwantes
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0873 , H01L21/266 , H01L29/161 , H01L29/165 , H01L29/66681 , H01L29/7824
摘要： High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.
摘要翻译：提供了高压场效应晶体管，其包括漏极端子，源极端子，主体端子和栅极端子。与栅极氧化物相邻的栅极氧化物和栅电极连接到栅极端子。第一导电类型的漏极半导体区域连接到漏极端子。第一导电类型的源极半导体区域连接到源极端子。第二导电类型的主体端子半导体区域连接到主体端子。第二导电类型的体半导体区域部分地与栅极氧化物相邻以形成沟道并且邻近体终端半导体区域。第一导电类型的漂移半导体区域与漏极半导体区域和体半导体区域相邻，其中在漂移半导体区域中，在远离体半导体区域的区域中形成势垒。

8. 发明申请

US20070235779A1 Lateral DMOS transistor and method for the production thereof 失效
标题翻译：侧面DMOS晶体管及其制造方法
公开(公告)号：US20070235779A1
公开(公告)日：2007-10-11
申请号：US11730514
申请日：2007-04-02
申请人： Franz Dietz , Volker Dudek , Thomas Hoffmann , Michael Graf , Stefan Schwantes
发明人： Franz Dietz , Volker Dudek , Thomas Hoffmann , Michael Graf , Stefan Schwantes
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/66659 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.
摘要翻译：提供了一种横向DMOS晶体管，其包括由第一导电类型的半导体材料制成的MOS二极管，第二导电类型的源极区域和第二导电类型的漏极区域，其为通过由第二导电类型的半导体材料制成的漂移区域与MOS二极管分开，所述漂移区域至少部分被还覆盖MOS二极管的半导体材料的介电栅极层覆盖。介电栅极层包括第一厚度的第一区域和第二厚度的第二区域。第一区域覆盖MOS二极管的半导体材料，第二区域布置在漂移区域上。从第一厚度到第二厚度发生转变，使得朝向MOS二极管定向的漂移区的边缘区域布置在栅极层的第二区域的下方。本发明还涉及一种用于生产这些类型的DMOS晶体管的方法。

9. 发明申请

US20070221965A1 DMOS device with sealed channel processing 有权
标题翻译： DMOS设备密封通道处理
公开(公告)号：US20070221965A1
公开(公告)日：2007-09-27
申请号：US11386316
申请日：2006-03-22
申请人： Gayle Miller , Irwin Rathbun , Stefan Schwantes , Michael Graf , Volker Dudek
发明人： Gayle Miller , Irwin Rathbun , Stefan Schwantes , Michael Graf , Volker Dudek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/2253 , H01L21/26586 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.
摘要翻译：一种制造电子设备的方法和由此产生的电子设备。该方法包括在衬底上形成衬垫氧化物层，在衬垫氧化物层上形成氮化硅层，并在氮化硅层上形成顶部氧化物层。然后在衬底的第一部分中形成第一掺杂区域。除去顶部氧化物层的第一部分; 使用顶部氧化物层的剩余部分来对准第二掺杂剂掩模，并且形成第二掺杂剂区域。退火步骤驱动掺杂剂，但是氧化物扩散到衬底受到氮化硅层的限制; 因此，氮化硅层确保在退火步骤之后，在靠近掺杂剂区域的区域中硅的最上表面基本上是平面的。

10. 发明授权

US07001804B2 Method of producing active semiconductor layers of different thicknesses in an SOI wafer 有权
标题翻译：在SOI晶片中制造不同厚度的有源半导体层的方法
公开(公告)号：US07001804B2
公开(公告)日：2006-02-21
申请号：US11048963
申请日：2005-01-31
申请人： Franz Dietz , Volker Dudek , Michael Graf
发明人： Franz Dietz , Volker Dudek , Michael Graf
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/76264 , H01L21/84
摘要： An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.
摘要翻译：处理包括绝缘层上的有源半导体材料层的SOI晶片，以在其上形成分别具有不同厚度并且垂直和横向绝缘的第一和第二有源半导体区域。在该过程中，沟槽被蚀刻到SOI晶片中，种子开口形成在沟槽的底部以到达下面的活性材料层，沟槽填充有从种子开口进行的外延生长的半导体材料，一些外延去除生长材料以形成第二有源区，并且提供氧化物层，使得第二有源区域与由有源半导体材料层的剩余部分形成的第一有源区域横向和垂直地绝缘。

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