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1. 发明申请

US20090206452A1 METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中用共平面表面形成自对准双阱的方法和系统
公开(公告)号：US20090206452A1
公开(公告)日：2009-08-20
申请号：US12426921
申请日：2009-04-20
申请人： Gayle W. Miller, JR. , Bryan D. Sendelweck
发明人： Gayle W. Miller, JR. , Bryan D. Sendelweck
IPC分类号： H01L29/02
CPC分类号： H01L21/823892 , H01L21/324
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。所述方法和系统包括提供至少一个干涉层并提供覆盖半导体器件的第一部分并露出半导体器件的第二部分的第一掩模。半导体器件的第一和第二部分相邻。该方法和系统还包括在提供第一掩模之后将第一阱注入半导体器件的第二部分。该方法和系统还包括提供第二掩模。干涉层被配置为使得在覆盖曝光期间的能量产生露出第一部分并覆盖半导体器件的第二部分的第二掩模。该方法和系统还包括在提供第二掩模之后将第二阱注入半导体器件的第一部分。

2. 发明申请

US20080166862A1 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device 有权
标题翻译：用于在半导体器件中产生具有共面表面的自对准双阱的方法和系统
公开(公告)号：US20080166862A1
公开(公告)日：2008-07-10
申请号：US11650164
申请日：2007-01-05
申请人： Gayle W. Miller , Bryan D. Sendelweck
发明人： Gayle W. Miller , Bryan D. Sendelweck
IPC分类号： H01L21/426
CPC分类号： H01L21/823892 , H01L21/324
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。所述方法和系统包括提供至少一个干涉层并提供覆盖半导体器件的第一部分并露出半导体器件的第二部分的第一掩模。半导体器件的第一和第二部分相邻。该方法和系统还包括在提供第一掩模之后将第一阱注入半导体器件的第二部分。该方法和系统还包括提供第二掩模。干涉层被配置为使得在覆盖曝光期间的能量产生露出第一部分并覆盖半导体器件的第二部分的第二掩模。该方法和系统还包括在提供第二掩模之后将第二阱注入半导体器件的第一部分。

3. 发明授权

US07541250B2 Method for forming a self-aligned twin well region with simplified processing 有权
标题翻译：用于形成具有简化处理的自对准双阱区域的方法
公开(公告)号：US07541250B2
公开(公告)日：2009-06-02
申请号：US11371258
申请日：2006-03-07
申请人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
发明人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
IPC分类号： H01L21/20
CPC分类号： H01L21/2256 , H01L21/266 , H01L21/823493 , H01L21/823892
摘要： A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
摘要翻译：提供了一种形成自对准双阱区域的方法。该方法包括将第一阱类型的掺杂物质注入到DHL中，使得其分布保持停留在硅衬底上方的DHL中，使用光致抗蚀剂掩模蚀刻掉DHL的一部分，将第二阱类型掺杂物质注入到硅衬底通过蚀刻而暴露，并将第一阱类掺杂物质的一部分移动到硅衬底中。

4. 发明授权

US08138578B2 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device 有权
标题翻译：用于在半导体器件中产生具有共面表面的自对准双阱的方法和系统
公开(公告)号：US08138578B2
公开(公告)日：2012-03-20
申请号：US12426921
申请日：2009-04-20
申请人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
发明人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
IPC分类号： H01L23/58
CPC分类号： H01L21/823892 , H01L21/324
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。所述方法和系统包括提供至少一个干涉层并提供覆盖半导体器件的第一部分并露出半导体器件的第二部分的第一掩模。半导体器件的第一和第二部分相邻。该方法和系统还包括在提供第一掩模之后将第一阱注入半导体器件的第二部分。该方法和系统还包括提供第二掩模。干涉层被配置为使得在覆盖曝光期间的能量产生露出第一部分并覆盖半导体器件的第二部分的第二掩模。该方法和系统还包括在提供第二掩模之后将第二阱注入半导体器件的第一部分。

5. 发明授权

US07642181B2 LOCOS self-aligned twin well with a co-planar silicon surface 有权
标题翻译： LOCOS自对准双井与共面硅表面
公开(公告)号：US07642181B2
公开(公告)日：2010-01-05
申请号：US11343179
申请日：2006-01-30
申请人： Gayle W. Miller, Jr. , Irwin D. Rathbun , Bryan D. Sendelweck , Thomas S. Moss, III
发明人： Gayle W. Miller, Jr. , Irwin D. Rathbun , Bryan D. Sendelweck , Thomas S. Moss, III
IPC分类号： H01L21/425
CPC分类号： H01L21/823892
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。该方法和系统包括屏蔽设备的第一部分，使得设备的第二部分被暴露。牺牲层在器件的第一部分上具有第一部分，在器件的第二部分上具有第二部分。在一个方面，氧化停止层可以在牺牲层的下方。该方法和系统包括在装置的第二部分中注入第一阱，在第一阱被注入之后露出装置的第一部分，以及在曝光之后氧化牺牲层的第二部分。所述方法和系统还包括在第二阱被植入之后，在将器件氧化和平坦化之后，将第二阱注入器件的第一部分。

6. 发明授权

US07521312B2 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device 有权
标题翻译：用于在半导体器件中产生具有共面表面的自对准双阱的方法和系统
公开(公告)号：US07521312B2
公开(公告)日：2009-04-21
申请号：US11650164
申请日：2007-01-05
申请人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
发明人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L21/324
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。所述方法和系统包括提供至少一个干涉层并提供覆盖半导体器件的第一部分并露出半导体器件的第二部分的第一掩模。半导体器件的第一和第二部分相邻。该方法和系统还包括在提供第一掩模之后将第一阱注入半导体器件的第二部分。该方法和系统还包括提供第二掩模。干涉层被配置为使得在覆盖曝光期间的能量产生露出第一部分并覆盖半导体器件的第二部分的第二掩模。该方法和系统还包括在提供第二掩模之后将第二阱注入半导体器件的第一部分。

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