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    • 2. 发明授权
    • System and method for conditionally sending a request for data to a home node
    • 用于有条件地向家庭节点发送数据请求的系统和方法
    • US08438337B1
    • 2013-05-07
    • US12571230
    • 2009-09-30
    • Gaurav GargDavid T. Hass
    • Gaurav GargDavid T. Hass
    • G06F12/00
    • G06F12/0815G06F12/0813G06F12/0831G06F12/084G06F2212/1024G06F2212/2542
    • A system and method are provided for sharing data between a network including one or more network nodes. The network includes a number of individual network nodes and a home network node communicating with one another. The individual network nodes and the home network node include a plurality of processors and memory caches. The memory caches consist of private caches corresponding to individual processors, as well as shared caches which are shared among the plurality of processors of an individual node and accessible by the processors of the other network nodes. Each network node is capable of executing a hierarchy of data requests that originate in the private caches of an individual local network node. If no cache hits occur within the local network node, a conditional request is sent to the home network node to request data through the shared caches of the other network nodes.
    • 提供了一种用于在包括一个或多个网络节点的网络之间共享数据的系统和方法。 网络包括多个单独的网络节点和彼此通信的家庭网络节点。 各个网络节点和家庭网络节点包括多个处理器和存储器高速缓存。 存储器高速缓存由对应于各个处理器的专用高速缓存组成,以及在单个节点的多个处理器之间共享且可由其他网络节点的处理器访问的共享高速缓存。 每个网络节点能够执行源自个别本地网络节点的专用高速缓存中的数据请求的层次。 如果在本地网络节点内没有发生高速缓存命中,则向家庭网络节点发送条件请求,以通过其他网络节点的共享缓存来请求数据。
    • 4. 发明授权
    • Performance of a stride-based prefetcher on an out-of-order processing unit (CPU)
    • 基于步幅的预取器在无序中央处理单元(CPU)上的性能
    • US08949522B1
    • 2015-02-03
    • US13165736
    • 2011-06-21
    • Gaurav GargDavid T. Hass
    • Gaurav GargDavid T. Hass
    • G06F13/00
    • G06F13/385
    • Systems, apparatusses, and methods are disclosed for improving performance of a stride-based prefetcher on an out-of-order central processing unit (CPU). The present disclosure teaches a processor system that employs out-of-order stride prefetch units. The out-of-order stride prefetch units are utilized for issuing prefetches for out-of-order stride access patterns. In one or more embodiments, the out-of-order stride prefetch units examine the offsets between past virtual address (VA) accesses and the directions of the past VA accesses in order to generate an estimate of the underlying VA access stride of the executed program code (PC). In at least one embodiment, the out-of-order stride prefetch units use the estimate of the VA access stride in order to generate a prediction of future VA accesses. In some embodiments, after the out-of-order stride prefetch units have generated the prediction of future VA accesses, the out-of-order stride prefetch units prefetch the predicted future VA accesses.
    • 公开了用于改善无序中央处理单元(CPU)上的基于步长的预取器的性能的系统,装置和方法。 本公开教导了采用无序步长预取单元的处理器系统。 无序步幅预取单元用于发出无序步进访问模式的预取。 在一个或多个实施例中,无序步长预取单元检查过去虚拟地址(VA)访问与过去VA访问的方向之间的偏移量,以便生成执行程序的基本VA访问步幅的估计 代码(PC)。 在至少一个实施例中,无序步长预取单元使用VA访问步幅的估计,以便生成将来VA访问的预测。 在一些实施例中,在无序步幅预取单元已经产生未来VA访问的预测之后,无序步幅预取单元预取预测的未来VA访问。