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1. 发明授权

US6046938A Structure of a flash memory 有权
标题翻译：闪存结构
公开(公告)号：US6046938A
公开(公告)日：2000-04-04
申请号：US191326
申请日：1998-11-13
申请人： Gary Hong , Wenchi Ting , Joe Ko
发明人： Gary Hong , Wenchi Ting , Joe Ko
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0416
摘要： A structure of a flash memory is disclosed. The flash memory includes a common drain, a memory unit which has at least one memory cell, and a depletion mode selector transistor. The depletion mode selector transistor isolates the common drain and the memory unit. Two terminals the depletion mode selector transistor are coupled to the common drain and the memory unit, respectively.
摘要翻译：公开了闪速存储器的结构。闪速存储器包括公共漏极，具有至少一个存储单元的存储器单元和耗尽型选择晶体管。耗尽型选择器晶体管将公共漏极和存储器单元隔离。耗尽型选择晶体管的两个端子分别耦合到公共漏极和存储器单元。

2. 发明授权

US5852313A Flash memory cell structure having a high gate-coupling coefficient and a select gate 失效
标题翻译：具有高栅极耦合系数和选择栅极的闪存单元结构
公开(公告)号：US5852313A
公开(公告)日：1998-12-22
申请号：US967940
申请日：1997-11-12
申请人： Gary Hong , Patrick Wang , Wenchi Ting
发明人： Gary Hong , Patrick Wang , Wenchi Ting
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/115
摘要： A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.
摘要翻译：一种闪速存储单元结构，包括具有形成在其上的第一晶体管和第二晶体管的半导体衬底。第一晶体管具有堆叠栅极和第一源极/漏极区域，其中堆叠栅极还包括浮置栅极和控制栅极。控制栅极形成在浮动栅极上方。第二晶体管与第一晶体管串联电连接。第二晶体管用作选择晶体管，并且包括栅极和第二源极/漏极区域。

3. 发明授权

US6008522A Structure of buried bit line 失效
标题翻译：埋地线的结构
公开(公告)号：US6008522A
公开(公告)日：1999-12-28
申请号：US113844
申请日：1998-07-10
申请人： Gary Hong , Yau-Kae Sheu , Wenchi Ting
发明人： Gary Hong , Yau-Kae Sheu , Wenchi Ting
IPC分类号： H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/112 , H01L29/76
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/112 , H01L27/11213 , Y10S257/91
摘要： The structure of a buried bit line. A substrate is provided and a trench is, formed within the substrate. Next, a trench insulating layer is located on a portion of the trench surface to expose a top corner of the trench. Then, a first conductive layer is fills the trench and forms a surface. Afterwards, a second conductive layer is formed on the surface and fills the trench, wherein the second conductive layer makes contact with the top corner, and a shallow junction region is located at the top corner and makes contact with the second conductive layer.
摘要翻译：埋地线的结构。提供衬底并且在衬底内形成沟槽。接下来，沟槽绝缘层位于沟槽表面的一部分上以暴露沟槽的顶角。然后，第一导电层填充沟槽并形成表面。之后，在表面上形成第二导电层并填充沟槽，其中第二导电层与顶角接触，并且浅结区位于顶角处并与第二导电层接触。

4. 发明授权

US5882972A Method of fabricating a buried bit line 失效
标题翻译：掩埋位线的制造方法
公开(公告)号：US5882972A
公开(公告)日：1999-03-16
申请号：US114005
申请日：1998-07-10
申请人： Gary Hong , Yau-Kae Sheu , Wenchi Ting
发明人： Gary Hong , Yau-Kae Sheu , Wenchi Ting
IPC分类号： H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/112 , H01L21/8236
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/112 , H01L27/11213 , Y10S257/91
摘要： A method of fabricating a buried bit line. An insulating layer is formed on a substrate, a trench is formed within the substrate by patterning the insulating layer and the substrate and then a liner oxide is formed on the trench surface. Then, a first conductive layer is formed on the insulating layer to cover the liner oxide layer and fills the trench. A portion of the first conductive layer is removed, exposing a portion of the liner oxide layer. Next, the exposed liner oxide layer is removed to form a space which, along with the trench, is filled with a second conductive layer on the insulating layer. Ion implantation and annealing is performed to form a shallow junction region in the substrate and the shallow junction region makes contact with the second conductive layer. A portion of the second conductive layer is then removed and the remaining second conductive layer fills the trench wherein the remaining second conductive layer is electrically coupled with the first conductive layer and the shallow junction region.
摘要翻译：一种制造掩埋位线的方法。在衬底上形成绝缘层，通过图案化绝缘层和衬底，在衬底内形成沟槽，然后在沟槽表面上形成衬垫氧化物。然后，在绝缘层上形成第一导电层以覆盖衬里氧化物层并填充沟槽。去除第一导电层的一部分，暴露衬里氧化物层的一部分。接下来，去除暴露的衬垫氧化物层以形成与沟槽一起在绝缘层上填充有第二导电层的空间。进行离子注入和退火以在衬底中形成浅结区域，并且浅结区域与第二导电层接触。然后去除第二导电层的一部分，剩余的第二导电层填充沟槽，其中剩余的第二导电层与第一导电层和浅结区域电耦合。

5. 发明授权

US06436787B1 Method of forming crown-type MIM capacitor integrated with the CU damascene process 有权
标题翻译：与CU镶嵌工艺集成的冠型MIM电容器的形成方法
公开(公告)号：US06436787B1
公开(公告)日：2002-08-20
申请号：US09912735
申请日：2001-07-26
申请人： Wong-Cheng Shih , Tzyh-Cheang Lee , Wenchi Ting , Chih-Hsien Lin , Shyh-Chyi Wong
发明人： Wong-Cheng Shih , Tzyh-Cheang Lee , Wenchi Ting , Chih-Hsien Lin , Shyh-Chyi Wong
IPC分类号： H01L2120
CPC分类号： H01L28/55 , H01L21/3212 , H01L28/75 , H01L28/91
摘要： A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening. The layers are polished back to leave the first metal layer, the dielectric layer, the first and second barrier metal layers, and the second metal layer only within the damascene opening wherein the first metal layer forms a bottom electrode, the dielectric layer forms a capacitor dielectric, and the second metal layer forms a top electrode to complete fabrication of a crown-type capacitor in the fabrication of an integrated circuit device.
摘要翻译：描述了使用集成铜镶嵌工艺制造增加的电容金属 - 绝缘体 - 金属电容器的方法。提供覆盖半导体衬底的接触节点。沉积在接触节点上的金属间介电层。通过金属间介质层向接触节点形成镶嵌开口。第一金属层形成在镶嵌开口的底部和侧壁上并覆盖金属间介电层。第一阻挡金属层被沉积在第一金属层上。介电层被覆在第一阻挡金属层上方。沉积在电介质层上的第二阻挡金属层。形成第二金属层，覆盖第二阻挡金属层并完全填充镶嵌开口。这些层被抛光回去，以留下第一金属层，电介质层，第一和第二阻挡金属层和第二金属层，仅在镶嵌开口内，其中第一金属层形成底部电极，电介质层形成电容器电介质，并且第二金属层形成顶部电极，以在集成电路器件的制造中完成冠型电容器的制造。

6. 发明授权

US5844271A Single layer polycrystalline silicon split-gate EEPROM cell having a buried control gate 失效
标题翻译：具有埋置控制栅极的单层多晶硅分离栅极EEPROM单元
公开(公告)号：US5844271A
公开(公告)日：1998-12-01
申请号：US517495
申请日：1995-08-21
申请人： Rakesh Sethi , Wenchi Ting
发明人： Rakesh Sethi , Wenchi Ting
IPC分类号： G11C16/04 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L29/7885 , G11C16/0425 , H01L27/115 , H01L29/42324
摘要： An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel formed therebetween. Silicon dioxide is disposed over the drain, channel and source regions wherein the oxide overlying the drain and a portion of the channel is thicker compared to the thickness of the oxide overlying the remainder of the channel and the source. A layer of polycrystalline silicon is disposed over the channel. The buried N-plate control gate is spaced laterally from the source, drain, and channel regions. The floating gate overlying the channel extends also over the buried N-plate control gate. The split gate structure effectively realizes a pair of in-series gates, each having a different threshold voltage in accordance with the thickness of the oxide used. The voltages applied to the N-plate region are capacitively coupled to the floating gate. The potential on the floating gate in turn causes activation of the transistors formed by the split-gate structure, depending on the existing charge on the floating gate.
摘要翻译：电可擦除可编程只读存储器（EEPROM）单元包括分离栅极读取晶体管和掩埋N板控制栅极。分离栅晶体管包括形成在P型硅衬底中的漏极和源极区域，其间形成有沟道。二氧化硅设置在漏极，沟道和源极区域之上，其中覆盖漏极的氧化物和沟道的一部分与覆盖沟道和源的其余部分的氧化物的厚度相比更厚。多晶硅层设置在通道上。掩埋的N极板控制栅极与源极，漏极和沟道区域横向间隔开。覆盖通道的浮动栅极还在掩埋的N极板控制栅极上延伸。分离栅极结构有效地实现了一对串联栅极，每对栅极具有根据所用氧化物的厚度的不同阈值电压。施加到N板区域的电压电容耦合到浮动栅极。浮动栅极上的电位依次由浮栅的现有电荷导致由分闸门结构形成的晶体管的激活。

7. 发明授权

US5751631A Flash memory cell and a new method for sensing the content of the new memory cell 失效
公开(公告)号：US5751631A
公开(公告)日：1998-05-12
申请号：US735384
申请日：1996-10-21
申请人： David K. Y. Liu , Wenchi Ting
发明人： David K. Y. Liu , Wenchi Ting
IPC分类号： G11C16/04 , G11C16/26 , H01L27/115 , H01L27/12
CPC分类号： H01L27/1203 , G11C16/0483 , G11C16/26 , H01L27/115
摘要： A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.

8. 发明授权

US06232183B1 Method for fabricating a flash memory 有权
标题翻译：制造闪存的方法
公开(公告)号：US06232183B1
公开(公告)日：2001-05-15
申请号：US09227680
申请日：1999-01-08
申请人： Hwi-Huang Chen , Wenchi Ting
发明人： Hwi-Huang Chen , Wenchi Ting
IPC分类号： H01L21336
CPC分类号： H01L29/66825
摘要： A method for fabricating a flash memory is disclosed, in which a stacked gate structure comprising a floating gate and a control gate on the substrate is first formed. Ions are implanted into the substrate at one side of the stacked gate. A drain having a heavily doped region and a lightly doped region are subsequently formed. Spacers one each side of the stacked gate structure are formed. By using a photoresist layer covering the spacer at the drain end, the spacer at the source end can be reduced by an etching process. The source region of the flash memory is formed by implanting ions into the substrate using the reduced spacer as a mask.
摘要翻译：公开了一种用于制造闪速存储器的方法，其中首先形成包括浮置栅极和基板上的控制栅极的堆叠栅极结构。离子在堆叠栅极的一侧被植入衬底中。随后形成具有重掺杂区和轻掺杂区的漏极。形成堆叠栅极结构的每一侧的间隔。通过使用在漏极端覆盖间隔物的光致抗蚀剂层，通过蚀刻工艺可以减少源极处的间隔物。通过使用还原间隔物作为掩模将离子注入到衬底中来形成闪存的源区。

9. 发明授权

US6091636A Flash memory cell and a new method for sensing the content of the new memory cell 失效
标题翻译：闪存单元和用于感测新存储单元的内容的新方法
公开(公告)号：US6091636A
公开(公告)日：2000-07-18
申请号：US417234
申请日：1998-03-26
申请人： David K. Y. Liu , Wenchi Ting
发明人： David K. Y. Liu , Wenchi Ting
IPC分类号： G11C16/04 , G11C16/26 , H01L27/115 , H01L27/12 , G11C16/06
CPC分类号： H01L27/1203 , G11C16/0483 , G11C16/26 , H01L27/115
摘要： A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.
摘要翻译：一种用于感测闪速存储器单元的内容的方法，以及适用于该新感测方案的新型闪存单元结构。在第一方面，半导体存储单元包括包含沟道区的轻掺杂n区; 覆盖所述n区的部分的第一绝缘层; 覆盖所述第一绝缘层的浮动栅极; 覆盖所述浮动栅极的第二绝缘层; 以及覆盖第二绝缘层的控制栅极。

10. 发明授权

US5814854A Highly scalable FLASH EEPROM cell 失效
标题翻译：高度可扩展的闪存EEPROM单元
公开(公告)号：US5814854A
公开(公告)日：1998-09-29
申请号：US711479
申请日：1996-09-09
申请人： David K. Y. Liu , Wenchi Ting
发明人： David K. Y. Liu , Wenchi Ting
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0416 , H01L29/7883
摘要： The present invention is directed toward a novel type of FLASH EEPROM cell that is highly scalable in size, easy to fabricate, reliable and capable of in-system programmability. The semiconductor memory cell comprises a lightly doped n- region including a channel region, a first insulating layer overlying portions of said n- region, and a floating gate overlying said first insulating layer. The cell further includes a second insulating layer overlying said floating gate and a control gate overlying second insulating layer.
摘要翻译：本发明涉及一种新型的FLASH EEPROM单元，其尺寸高度可扩展，易于制造，可靠并且能够进行系统可编程性。半导体存储单元包括轻掺杂n-区，包括沟道区，覆盖所述n-区的部分的第一绝缘层和覆盖所述第一绝缘层的浮动栅极。电池还包括覆盖所述浮动栅极的第二绝缘层和覆盖第二绝缘层的控制栅极。

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