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1. 发明授权

US4654857A Digital data processor with high reliability 失效
标题翻译：数字数据处理器具有高可靠性
公开(公告)号：US4654857A
公开(公告)日：1987-03-31
申请号：US762039
申请日：1985-08-02
申请人： Joseph E. Samson , Kenneth T. Wolff , Robert Reid , Gardner C. Hendrie , Daniel M. Falkoff , Ronald E. Dynneson , Daniel M. Clemson , Kurt F. Baty
发明人： Joseph E. Samson , Kenneth T. Wolff , Robert Reid , Gardner C. Hendrie , Daniel M. Falkoff , Ronald E. Dynneson , Daniel M. Clemson , Kurt F. Baty
IPC分类号： G06F11/18 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F13/00 , G06F13/374
CPC分类号： G06F11/1625 , G06F11/1641 , G06F11/2007 , G06F13/374 , G06F11/10 , G06F11/20
摘要： A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
摘要翻译：容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

2. 发明授权

US4750177A Digital data processor apparatus with pipelined fault tolerant bus protocol 失效
标题翻译：具有流水线容错总线协议的数字数据处理器
公开(公告)号：US4750177A
公开(公告)日：1988-06-07
申请号：US904827
申请日：1986-09-08
申请人： Gardner C. Hendrie , Kurt F. Baty , Ronald E. Dynneson , Daniel M. Falkoff , Robert Reid , Joseph E. Samson , Kenneth T. Wolff
发明人： Gardner C. Hendrie , Kurt F. Baty , Ronald E. Dynneson , Daniel M. Falkoff , Robert Reid , Joseph E. Samson , Kenneth T. Wolff
IPC分类号： G06F11/00 , G06F1/04 , G06F3/00 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/00
CPC分类号： G06F11/1625 , G06F11/1402 , G06F11/1604 , G06F11/2005 , G06F11/2007 , G06F11/2017 , G06F11/22 , G06F1/04 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
摘要翻译：容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

3. 发明授权

US4486826A Computer peripheral control apparatus 失效
标题翻译：电脑周边控制装置
公开(公告)号：US4486826A
公开(公告)日：1984-12-04
申请号：US307524
申请日：1981-10-01
申请人： Kenneth T. Wolff , Joseph E. Samson , Kurt F. Baty
发明人： Kenneth T. Wolff , Joseph E. Samson , Kurt F. Baty
IPC分类号： G06F11/18 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F13/00 , G06F13/374 , G06F15/16 , G06F15/06
CPC分类号： G06F11/1625 , G06F11/1641 , G06F11/2007 , G06F13/374 , G06F11/10 , G06F11/20
摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
摘要翻译：容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

4. 发明授权

US5243704A Optimized interconnect networks 失效
标题翻译：优化的互连网络
公开(公告)号：US5243704A
公开(公告)日：1993-09-07
申请号：US884257
申请日：1992-05-08
申请人： Kurt F. Baty , Charles J. Horvath, Jr. , Richard C. Clemson , Scott J. Bleiweiss , Kenneth T. Wolff
发明人： Kurt F. Baty , Charles J. Horvath, Jr. , Richard C. Clemson , Scott J. Bleiweiss , Kenneth T. Wolff
IPC分类号： G06F15/173
CPC分类号： G06F15/17343
摘要： A multinodal system is one-way interconnected, two-way interconnected or, more generally, (n)-way interconnected, where (n) is an integer. In a one-way interconnected system, only one connection element couples any two nodes. Or, put another way, only one communication path exists between every node and every other node. A two-way interconnected system, on the other hand, has two connection elements coupling each pair of nodes. Likewise, an (n)-way interconnected system provides (n) independent connection paths between each pair. Such systems are characteristic in that the relationship between the number of independent buses (b), the number of nodes (v), the number of ports (r), and the degree of interconnectedness (n) can be expressed by the equation ##EQU1## Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications.
摘要翻译：多节点系统是单向互连的，双向互连的，或者更一般地，（n）互连，其中（n）是整数。在单向互连系统中，只有一个连接元件耦合任何两个节点。或者换句话说，每个节点和每个其他节点之间只存在一条通信路径。另一方面，双向互连系统具有耦合每对节点的两个连接元件。同样，（n）互连系统在每对之间提供（n）个独立的连接路径。这样的系统的特征在于独立总线数量（b），节点数（v），端口数量（r）和互连度（n）之间的关系可以由公式双向和（n）路互连阵列可适用于容错通信。

5. 发明授权

US4931922A Method and apparatus for monitoring peripheral device communications 失效
标题翻译：用于监视外围设备通信的方法和装置
公开(公告)号：US4931922A
公开(公告)日：1990-06-05
申请号：US79218
申请日：1987-07-29
申请人： Kurt F. Baty , Joseph M. Lamb
发明人： Kurt F. Baty , Joseph M. Lamb
IPC分类号： G06F13/00 , G06F1/04 , G06F3/00 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/36 , G06F13/42
CPC分类号： G06F11/2017 , G06F11/0745 , G06F11/0793 , G06F11/1402 , G06F11/1604 , G06F11/1625 , G06F11/2005 , G06F11/2007 , G06F11/22 , G06F13/423 , G06F1/04 , G06F11/10 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： A fault-tolerant digital data processing system comprises at least a first peripheral controller communicating with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals. The first peripheral controller includes a first device interface element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The first device interface element also receives, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses. A second peripheral controller is coupled to the peripheral device bus for receiving the first and second input signals identically with the first peripheral controller. The second peripheral controller includes a second device interface element for applying at least one of those input signals to the second input/output controller. Circuitry is coupled to the first and second bus interface elements for responding to operational states of those elements to generate a signal indicative of their synchronous receipt of identical copies the first and second input signals.
摘要翻译：容错数字数据处理系统至少包括通过具有第一和第二输入/输出总线的外围设备总线与至少一个外围设备进行通信的第一外围控制器，每个总线承载数据，地址，控制和定时信号。第一外围控制器包括第一设备接口元件，用于同步地并且同时地向第一和第二输入/输出总线施加重复的信息信号以传输到外围设备。第一设备接口元件在没有故障的情况下还从第一和第二输入/输出总线同步并同时接收重复信息信号。第二外围控制器耦合到外围设备总线，用于与第一外围控制器相同地接收第一和第二输入信号。第二外围控制器包括用于将这些输入信号中的至少一个施加到第二输入/输出控制器的第二设备接口元件。电路耦合到第一和第二总线接口元件，用于响应这些元件的操作状态，以产生指示其同步接收相同副本的第一和第二输入信号的信号。

6. 发明授权

US4939643A Fault tolerant digital data processor with improved bus protocol 失效
标题翻译：具有改进总线协议的容错数字数据处理器
公开(公告)号：US4939643A
公开(公告)日：1990-07-03
申请号：US79223
申请日：1987-07-29
申请人： William L. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb
发明人： William L. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb
IPC分类号： G06F13/00 , G06F1/04 , G06F3/00 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/36 , G06F13/42
CPC分类号： G06F11/2017 , G06F11/0745 , G06F11/0793 , G06F11/1402 , G06F11/1604 , G06F11/1625 , G06F11/2005 , G06F11/2007 , G06F11/22 , G06F13/423 , G06F1/04 , G06F11/10 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： A fault-tolerant digital data processor includes a peripheral device controller for communicating with one or more peripheral devices over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing information. Each peripheral device includes a device interface for transferring information signals between the associated peripheral device and the peripheral bus. The peripheral device controller includes a strobe element connected with the first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define successive timing intervals for information transfers along the peripheral bus. Information transfers are normally effected by the transmission of duplicate information signals synchronously and simultaneously on the first and second input/output buses. A transfer cycle element includes a scanner cycle element to determine an operational state of at least one of the peripheral devices connected to the peripheral bus; a command cycle element for executing a command cycle for controlling operation of an attached peripheral device; a read cycle element for effecting the transfer of data signals from the peripheral device to the input/output controller; and a write cycle element for transferring data signals from the input/output controller an attached peripheral device.
摘要翻译：容错数字数据处理器包括外围设备控制器，用于通过具有第一和第二输入/输出总线的外围设备总线与一个或多个外围设备通信，每个外围设备总线承载数据，地址，控制和定时信息。每个外围设备包括用于在相关联的外围设备和外围总线之间传送信息信号的设备接口。外围设备控制器包括与第一和第二输入/输出总线连接的选通元件，用于在其上传输重复的，同步的和同时的选通信号。这些选通信号定义了沿着外围总线的信息传输的连续定时间隔。信息传送通常通过在第一和第二输入/输出总线上同步并同时传输重复信息信号来实现。转移循环元件包括扫描器循环元件，用于确定连接到外围总线的至少一个外围设备的操作状态; 用于执行用于控制附接的外围设备的操作的命令循环的命令循环元件; 用于实现数据信号从外围设备传送到输入/输出控制器的读周期元件; 以及用于从附加的外围设备的输入/输出控制器传送数据信号的写周期元件。

7. 发明授权

US4974150A Fault tolerant digital data processor with improved input/output controller 失效
标题翻译：具有容错输入/输出控制器的数字数据处理器
公开(公告)号：US4974150A
公开(公告)日：1990-11-27
申请号：US368125
申请日：1989-06-16
申请人： William F. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb
发明人： William F. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb
IPC分类号： G06F13/00 , G06F1/04 , G06F3/00 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/36 , G06F13/42
CPC分类号： G06F11/2017 , G06F11/0745 , G06F11/0793 , G06F11/1402 , G06F11/1604 , G06F11/1625 , G06F11/2005 , G06F11/2007 , G06F11/22 , G06F13/423 , G06F1/04 , G06F11/10 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.
摘要翻译：容错数字数据处理系统至少包括通过外围设备总线与至少一个外围设备进行通信的第一输入/输出控制器。外围总线包括第一和第二输入/输出总线，每个总线具有用于承载数据，地址，控制和定时信号的装置。输入/输出控制器包括用于同时地并且同时地向第一和第二输入/输出总线施加重复信息信号以传输到外围设备的元件。输入/输出控制器还包括总线接口元件，用于在不存在故障的情况下从第一和第二输入/输出总线同步并同时接收重复的信息信号。

8. 发明授权

US4974144A Digital data processor with fault-tolerant peripheral interface 失效
标题翻译：具有容错外设接口的数字数据处理器
公开(公告)号：US4974144A
公开(公告)日：1990-11-27
申请号：US368124
申请日：1989-06-16
申请人： William L. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb
发明人： William L. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb
IPC分类号： G06F13/00 , G06F1/04 , G06F3/00 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/36 , G06F13/42
CPC分类号： G06F11/2017 , G06F11/0745 , G06F11/0793 , G06F11/1402 , G06F11/1604 , G06F11/1625 , G06F11/2005 , G06F11/2007 , G06F11/22 , G06F13/423 , G06F1/04 , G06F11/10 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： A fault-tolerant digital data processing system comprises a first input-output controller which communicates with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals from the input/output controller to the peripheral device. A device interface is coupled to the first and second input/output buses and to an associated peripheral device for transferring information between the buses and the associated peripheral device. In normal operation, the device interface applies duplicate information signals synchronously and simultaneously to the input/output buses for transfer to the input/output controller. The device interface also receives, in the absence of fault, duplicative information signal synchronously and simultaneously from the first and second input/output buses.
摘要翻译：容错数字数据处理系统包括：第一输入 - 输出控制器，其通过具有第一和第二输入/输出总线的外围设备总线与至少一个外围设备进行通信，每个外围设备总线承载来自所述第一和第二输入/输出总线的数据，地址，控制和定时信号输入/输出控制器到外围设备。设备接口耦合到第一和第二输入/输出总线以及相关联的外围设备，用于在总线和相关联的外围设备之间传送信息。在正常操作中，设备接口同时同时向输入/输出总线应用重复信息信号，以传输到输入/输出控制器。设备接口还在不存在故障的情况下从第一和第二输入/输出总线同步并同时接收重复信息信号。

9. 发明授权

US4926315A Digital data processor with fault tolerant peripheral bus communications 失效
标题翻译：具有容错外设总线通信的数字数据处理器
公开(公告)号：US4926315A
公开(公告)日：1990-05-15
申请号：US79297
申请日：1987-07-29
申请人： William L. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb , John E. McNamara
发明人： William L. Long , Robert F. Wambach , Kurt F. Baty , Joseph M. Lamb , John E. McNamara
IPC分类号： G06F13/00 , G06F1/04 , G06F3/00 , G06F11/00 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/36 , G06F13/42
CPC分类号： G06F11/2017 , G06F11/0745 , G06F11/0793 , G06F11/1402 , G06F11/1604 , G06F11/1625 , G06F11/2005 , G06F11/2007 , G06F11/22 , G06F13/423 , G06F1/04 , G06F11/10 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.
摘要翻译：容错数字数据处理系统至少包括通过外围设备总线与至少一个外围设备进行通信的第一输入/输出控制器。外围总线包括第一和第二输入/输出总线，每个总线具有用于承载数据，地址，控制和定时信号的装置。输入/输出控制器包括用于同时地并且同时地向第一和第二输入/输出总线施加重复信息信号以传输到外围设备的元件。输入/输出控制器还包括总线接口元件，用于在不存在故障的情况下从第一和第二输入/输出总线同步并同时接收重复的信息信号。

10. 发明授权

US4920540A Fault-tolerant digital timing apparatus and method 失效
标题翻译：容错数字定时装置及方法
公开(公告)号：US4920540A
公开(公告)日：1990-04-24
申请号：US18629
申请日：1987-02-25
申请人： Kurt F. Baty
发明人： Kurt F. Baty
IPC分类号： G06F11/00 , G06F1/04 , G06F11/14 , G06F11/16 , G06F11/20 , G06F11/22
CPC分类号： G06F11/1604 , G06F11/1402 , G06F11/1625 , G06F11/2005 , G06F11/2007 , G06F11/2017 , G06F11/22 , G06F1/04 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： Computer timing apparatus enables two clock elements to produce a single stream of timing pulses, without interruption, when both elements are operating normally, and when one element fails. The apparatus incorporates a multi-stable stage and an output logic stage. The multi-stable stage detects state transitions in the input signals of each clock element and generates a corresponding clock-tracking signal which can disable the output of the corresponding clock from propagating through the output logic. The output logic stage logically combines each clock signal with its corresponding clock-tracking signal, and logically combines the resultant signal to produce a single stream of output signals responsive to a next transition produced by either of the two clock elements.

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