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1. 发明授权

US4654857A Digital data processor with high reliability 失效
标题翻译：数字数据处理器具有高可靠性
公开(公告)号：US4654857A
公开(公告)日：1987-03-31
申请号：US762039
申请日：1985-08-02
申请人： Joseph E. Samson , Kenneth T. Wolff , Robert Reid , Gardner C. Hendrie , Daniel M. Falkoff , Ronald E. Dynneson , Daniel M. Clemson , Kurt F. Baty
发明人： Joseph E. Samson , Kenneth T. Wolff , Robert Reid , Gardner C. Hendrie , Daniel M. Falkoff , Ronald E. Dynneson , Daniel M. Clemson , Kurt F. Baty
IPC分类号： G06F11/18 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F13/00 , G06F13/374
CPC分类号： G06F11/1625 , G06F11/1641 , G06F11/2007 , G06F13/374 , G06F11/10 , G06F11/20
摘要： A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
摘要翻译：容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

2. 发明授权

US4750177A Digital data processor apparatus with pipelined fault tolerant bus protocol 失效
标题翻译：具有流水线容错总线协议的数字数据处理器
公开(公告)号：US4750177A
公开(公告)日：1988-06-07
申请号：US904827
申请日：1986-09-08
申请人： Gardner C. Hendrie , Kurt F. Baty , Ronald E. Dynneson , Daniel M. Falkoff , Robert Reid , Joseph E. Samson , Kenneth T. Wolff
发明人： Gardner C. Hendrie , Kurt F. Baty , Ronald E. Dynneson , Daniel M. Falkoff , Robert Reid , Joseph E. Samson , Kenneth T. Wolff
IPC分类号： G06F11/00 , G06F1/04 , G06F3/00 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/00
CPC分类号： G06F11/1625 , G06F11/1402 , G06F11/1604 , G06F11/2005 , G06F11/2007 , G06F11/2017 , G06F11/22 , G06F1/04 , G06F11/1629 , G06F11/1666 , G06F11/20
摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
摘要翻译：容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

3. 发明授权

US4486826A Computer peripheral control apparatus 失效
标题翻译：电脑周边控制装置
公开(公告)号：US4486826A
公开(公告)日：1984-12-04
申请号：US307524
申请日：1981-10-01
申请人： Kenneth T. Wolff , Joseph E. Samson , Kurt F. Baty
发明人： Kenneth T. Wolff , Joseph E. Samson , Kurt F. Baty
IPC分类号： G06F11/18 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F13/00 , G06F13/374 , G06F15/16 , G06F15/06
CPC分类号： G06F11/1625 , G06F11/1641 , G06F11/2007 , G06F13/374 , G06F11/10 , G06F11/20
摘要： A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
摘要翻译：容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输，包括处理器单元和存储器单元以及一个或多个外围控制单元。在总线结构和每个单元中，系统的信息处理部分可以具有重复的伙伴。错误检测器检查总线结构和每个系统单元的操作，仅在无故障总线导体和无故障单元之间提供信息传输。计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。模块的单元检查输入和输出信号是否有错误，向其他模块单元发出检测到的错误信号，并禁止单元向总线结构发送潜在的错误信息。

4. 发明授权

US5243704A Optimized interconnect networks 失效
标题翻译：优化的互连网络
公开(公告)号：US5243704A
公开(公告)日：1993-09-07
申请号：US884257
申请日：1992-05-08
申请人： Kurt F. Baty , Charles J. Horvath, Jr. , Richard C. Clemson , Scott J. Bleiweiss , Kenneth T. Wolff
发明人： Kurt F. Baty , Charles J. Horvath, Jr. , Richard C. Clemson , Scott J. Bleiweiss , Kenneth T. Wolff
IPC分类号： G06F15/173
CPC分类号： G06F15/17343
摘要： A multinodal system is one-way interconnected, two-way interconnected or, more generally, (n)-way interconnected, where (n) is an integer. In a one-way interconnected system, only one connection element couples any two nodes. Or, put another way, only one communication path exists between every node and every other node. A two-way interconnected system, on the other hand, has two connection elements coupling each pair of nodes. Likewise, an (n)-way interconnected system provides (n) independent connection paths between each pair. Such systems are characteristic in that the relationship between the number of independent buses (b), the number of nodes (v), the number of ports (r), and the degree of interconnectedness (n) can be expressed by the equation ##EQU1## Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications.
摘要翻译：多节点系统是单向互连的，双向互连的，或者更一般地，（n）互连，其中（n）是整数。在单向互连系统中，只有一个连接元件耦合任何两个节点。或者换句话说，每个节点和每个其他节点之间只存在一条通信路径。另一方面，双向互连系统具有耦合每对节点的两个连接元件。同样，（n）互连系统在每对之间提供（n）个独立的连接路径。这样的系统的特征在于独立总线数量（b），节点数（v），端口数量（r）和互连度（n）之间的关系可以由公式双向和（n）路互连阵列可适用于容错通信。

5. 发明授权

US4395663A Circuit and method of linearity correction for CRT deflection circuits 失效
标题翻译： CRT偏转电路的线性校正电路及方法
公开(公告)号：US4395663A
公开(公告)日：1983-07-26
申请号：US213265
申请日：1980-12-05
申请人： Gerald Manktelow , Kenneth T. Wolff
发明人： Gerald Manktelow , Kenneth T. Wolff
IPC分类号： H03K4/69 , H03K4/90 , H01J29/70 , H01J29/76
CPC分类号： H03K4/90 , H03K4/696
摘要： Electronic apparatus and method is disclosed for generating a linearity correction signal for use in or with a CRT electron beam deflection circuit. In a preferred embodiment, transistor is used to vary the parameters of a multiple feedback infinite gain bandpass filter such that the filter is essentially on the point of oscillation during trace, but is highly damped during retrace.
摘要翻译：公开了用于产生用于CRT电子束偏转电路或与CRT电子束偏转电路一起使用的线性校正信号的电子设备和方法。在优选实施例中，晶体管用于改变多反馈无限增益带通滤波器的参数，使得滤波器基本上在跟踪期间在振荡点上，但在回扫期间是高度阻尼的。

6. 发明授权

US4377810A Light pen detection circuit and method 失效
标题翻译：光笔检测电路及方法
公开(公告)号：US4377810A
公开(公告)日：1983-03-22
申请号：US213244
申请日：1980-12-04
申请人： Kenneth T. Wolff
发明人： Kenneth T. Wolff
IPC分类号： G06F3/038 , G09G1/16
CPC分类号： G06F3/0386
摘要： Electronic apparatus and method for determining location of the sensing aperture of a light pen on the face of a raster scan monochrome CRT is disclosed. In a preferred embodiment, logic circuitry and cascaded counters are used to determine position information for the earliest horizontal detection of light during each frame. Apparatus is included for retaining the position information and making it available to the CRT processor for use in generating a cursor.
摘要翻译：公开了一种用于确定光笔在光栅扫描单色CRT的表面上的感测孔的位置的电子设备和方法。在优选实施例中，逻辑电路和级联计数器用于确定在每个帧期间最早的水平检测光的位置信息。包括用于保持位置信息并使其可用于CRT处理器用于生成光标的装置。

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