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1. 发明申请

US20070170489A1 Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process 审中-公开
标题翻译：增加在单门逻辑过程中制造的非易失性存储器的电荷保留的方法
公开(公告)号：US20070170489A1
公开(公告)日：2007-07-26
申请号：US11341881
申请日：2006-01-26
申请人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
发明人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42324
摘要： A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.
摘要翻译：具有增加的电荷保持的非易失性存储单元使用单栅极常规逻辑工艺在与逻辑器件相同的衬底上制造。在NVM单元的浮动栅极上形成硅化物阻挡介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。在这种情况下，硅化物阻挡介电层可以在形成硅化物之后变薄或去除。

2. 发明申请

US20100149874A1 NON-VOLATILE MEMORY APPARATUS AND METHOD WITH DEEP N-WELL 有权
标题翻译：非易失性存储器和方法与深度N-WELL
公开(公告)号：US20100149874A1
公开(公告)日：2010-06-17
申请号：US12334510
申请日：2008-12-14
申请人： WINGYU LEUNG , Gang-feng Fang
发明人： WINGYU LEUNG , Gang-feng Fang
IPC分类号： G11C16/02 , H01L21/336 , G11C16/06
CPC分类号： H01L27/11519 , G11C16/02 , G11C16/04 , H01L27/11521 , H01L27/11558
摘要： An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.
摘要翻译：公开了一种具有深N阱的电可编程和可擦除的非易失性存储单元的装置和方法，以将存储单元与衬底隔离开来。在一个实施例中，非易失性存储装置包括至少一个在P基板上制造的非易失性存储单元，其中深N阱位于P衬底中，而P阱和N阱位于深N井存储单元还包括位于N阱中的PMOS晶体管，其中PMOS晶体管包括PMOS栅极氧化物，以及位于P阱中的NMOS电容器。 NMOS电容器包括位于P阱中的N +耦合区域和NMOS栅极氧化物。存储单元还包括由PMOS晶体管和NMOS电容器叠加的多晶硅栅极构成的浮动栅极。

3. 发明授权

US07477546B2 Non-volatile memory embedded in a conventional logic process and methods for operating same 失效
公开(公告)号：US07477546B2
公开(公告)日：2009-01-13
申请号：US12021255
申请日：2008-01-28
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

4. 发明授权

US07391647B2 Non-volatile memory in CMOS logic process and method of operation thereof 失效
标题翻译： CMOS逻辑过程中的非易失性存储器及其操作方法
公开(公告)号：US07391647B2
公开(公告)日：2008-06-24
申请号：US11279382
申请日：2006-04-11
申请人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
发明人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C16/0416 , G11C16/10 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/7883
摘要： A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM cell also includes a PMOS access transistor located in a first n-type region, a PMOS control capacitor located in a second n-type region (separate from the first n-type region), and an NMOS programming transistor located in a p-type region. The floating gate electrode is a continuous electrode which extends over the active regions of the PMOS access transistor, the PMOS control capacitor and the NMOS programming transistor. Various array connections are provided for implementing arrays using this NVM cell. The PMOS access transistor and NMOS programming transistor can be replaced with an NMOS access transistor and a PMOS erase transistor, respectively, in an alternate embodiment.
摘要翻译：制造在半导体衬底上的非易失性存储器（NVM）单元，并且包括浮置栅极电极（至少部分地延伸到NVM单元的所有有源区域上）。 NVM单元还包括位于第一n型区域中的PMOS访问晶体管，位于第二n型区域（与第一n型区域分离）的PMOS控制电容器，以及位于p型区域中的NMOS编程晶体管型区域。浮置栅电极是在PMOS存取晶体管，PMOS控制电容器和NMOS编程晶体管的有源区域上延伸的连续电极。提供了各种阵列连接来实现使用该NVM单元的阵列。在替代实施例中，PMOS存取晶体管和NMOS编程晶体管可以分别被NMOS存取晶体管和PMOS擦除晶体管代替。

5. 发明授权

US07382658B2 Non-volatile memory embedded in a conventional logic process and methods for operating same 有权
标题翻译：嵌入在常规逻辑过程中的非易失性存储器及其操作方法
公开(公告)号：US07382658B2
公开(公告)日：2008-06-03
申请号：US11421986
申请日：2006-06-02
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C11/34 , G11C11/24
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
摘要翻译：一种包括单元阵列的非易失性存储器系统，每个单元具有存取晶体管和共享浮置栅极的电容器。每行中的存取晶体管被制造在独立的偏置区域中。在每行内，每个存取晶体管的源极耦合到对应的虚拟接地线，并且每个电容器结构耦合到对应的字线。或者，列中的每个存取晶体管的源极耦合到相应的虚拟接地线。在每列中，每个存取晶体管的漏极耦合到相应的位线。选择每行的存储单元通过带对带隧道进行编程。位线偏置可防止对该行的非选定单元进行编程。通过控制这些行的阱区电压，在未选择的行中防止编程。扇区擦除操作由Fowler-Nordheim隧道实现。

6. 发明授权

US07919367B2 Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process 有权
标题翻译：增加在单门逻辑过程中制造的非易失性存储器的电荷保留的方法
公开(公告)号：US07919367B2
公开(公告)日：2011-04-05
申请号：US12021229
申请日：2008-01-28
申请人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
发明人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
IPC分类号： H01L21/8238
CPC分类号： H01L29/7883 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.
摘要翻译：具有增加的电荷保持的非易失性存储单元使用单栅极常规逻辑工艺在与逻辑器件相同的衬底上制造。在NVM单元的浮动栅极上形成硅化物阻挡介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。在这种情况下，硅化物阻挡介质层可以在形成硅化物之后变薄或去除。

7. 发明授权

US07671401B2 Non-volatile memory in CMOS logic process 有权
标题翻译： CMOS逻辑过程中的非易失性存储器
公开(公告)号：US07671401B2
公开(公告)日：2010-03-02
申请号：US11262141
申请日：2005-10-28
申请人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
发明人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).
摘要翻译：一种方法，装置和系统，其中根据常规逻辑处理器制造的嵌入式存储器包括一个或多个电可更改的非易失性存储单元，每个具有编程晶体管，读取晶体管和控制电容器，其共享一个普通浮栅电极。编程晶体管和控制电容器的源极/漏极区域的不足扩散最大化。在一个实施例中，编程晶体管的源极/漏极区域通过晶体管穿通（或直接接触）电触发。

8. 发明授权

US07633811B2 Non-volatile memory embedded in a conventional logic process and methods for operating same 有权
公开(公告)号：US07633811B2
公开(公告)日：2009-12-15
申请号：US12021286
申请日：2008-01-28
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C11/34 , G11C16/04 , G11C11/24
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

9. 发明申请

US20080137438A1 Non-Volatile Memory Embedded In A Conventional Logic Process And Methods For Operating Same 有权
公开(公告)号：US20080137438A1
公开(公告)日：2008-06-12
申请号：US12021280
申请日：2008-01-28
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

10. 发明申请

US20080186778A1 Non-Volatile Memory Embedded In A Conventional Logic Process And Methods For Operating Same 有权
公开(公告)号：US20080186778A1
公开(公告)日：2008-08-07
申请号：US12021286
申请日：2008-01-28
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

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