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1. 发明申请

US20140299924A1 FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE 有权
标题翻译：形成替代盖结构的电介质层
公开(公告)号：US20140299924A1
公开(公告)日：2014-10-09
申请号：US14285852
申请日：2014-05-23
申请人： GLOBALFOUNFRIES SINGAPORE PTE. LTD. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong XIE , Balasubramanian PRANATHARTHI HARAN , David V. HORAK , Su Chen FAN
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/42376 , H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
摘要翻译：通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属，平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。

2. 发明申请

US20130309852A1 BORDERLESS CONTACT FOR AN ALUMINUM-CONTAINING GATE 有权
标题翻译：无铝接触门
公开(公告)号：US20130309852A1
公开(公告)日：2013-11-21
申请号：US13771930
申请日：2013-02-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sivananda K. KANAKASABAPATHY , David V. HORAK , Hemanth JAGANNATHAN
IPC分类号： H01L21/28
CPC分类号： H01L21/28 , H01L21/28008 , H01L21/76897 , H01L29/165 , H01L29/45 , H01L29/66545 , H01L29/66628
摘要： An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions.
摘要翻译：采用含铝材料形成替代栅电极。在平坦化介电层之上形成接触电介质材料层，其中嵌入有置换栅电极。通过接触层电介质层形成至少一个接触通孔。物理地暴露在至少一个接触通孔的底部的替代栅电极的任何部分是垂直凹陷的。替代栅电极内的含铝材料的物理暴露部分被氧化以形成介电铝化合物部分。随后，至少一个有源通孔腔中的每一个进一步延伸到下面的有源区，其可以是源区或漏区。形成在所述至少一个有源通路腔的每一个内的接触通孔结构可以通过介电铝化合物部分与替换栅极电隔离。

3. 发明申请

US20140061799A1 SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS 有权
标题翻译：具有自对准无源源/漏联系的硅绝缘体晶体管
公开(公告)号：US20140061799A1
公开(公告)日：2014-03-06
申请号：US14073581
申请日：2013-11-06
申请人： International Business Machines Corporation
发明人： Susan S. FAN , Balasubramanian S. HARAN , David V. HORAK , Charles W. KOBURGER
IPC分类号： H01L29/423 , H01L27/088 , H01L29/786 , H01L29/66 , H01L29/78
CPC分类号： H01L29/42384 , H01L21/76834 , H01L21/76897 , H01L27/088 , H01L27/1207 , H01L29/4908 , H01L29/66545 , H01L29/78 , H01L29/78651 , H01L29/78654
摘要： A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.
摘要翻译：提供了一种用于制造包括多个晶体管的集成电路的方法。在半导体层上形成替代栅极叠层，形成栅极间隔物，形成电介质层。去除虚拟栅极堆叠以形成空腔。在空腔中形成栅极电介质和功函数金属层。空腔填充有栅极导体。门导体和功函数金属层中的仅一个选择性地凹入。在凹部中形成氧化膜，使得其上表面与电介质层的上表面共面。氧化膜用于选择性地生长氧化物盖。形成并蚀刻层间电介质以形成用于源/漏接触的空腔。源极/漏极接触形成在接触腔中，源极/漏极触点的一部分直接位于氧化物盖上。

4. 发明申请

US20140068541A1 INTERCONNECT STRUCTURES AND METHODS FOR BACK END OF THE LINE INTEGRATION 有权
标题翻译：互联结构和线路整合后端的方法
公开(公告)号：US20140068541A1
公开(公告)日：2014-03-06
申请号：US14069855
申请日：2013-11-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： David V. HORAK , Charles W. KOBURGER, III , Shom PONOTH , Chih-Chao YANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L21/76834 , H01L21/76885
摘要： A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.
摘要翻译：形成半导体结构的方法包括形成牺牲导电材料层。该方法还包括在牺牲导电材料层中形成沟槽。该方法还包括在沟槽中形成导电特征。该方法还包括去除对导电特征有选择性的牺牲导电材料层。该方法还包括在导电特征周围形成绝缘层以将导电特征嵌入绝缘层。

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