专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160126145A1 LOW THRESHOLD VOLTAGE CMOS DEVICE 有权
标题翻译：低电压电压CMOS器件
公开(公告)号：US20160126145A1
公开(公告)日：2016-05-05
申请号：US14992739
申请日：2016-01-11
申请人： International Business Machines Corporation , Global Foundries Inc
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L29/10 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
摘要翻译：其中施加高k电介质的替代金属栅极工艺。高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。可以在高k电介质上形成伪栅极结构，并被蚀刻以在NMOS区域上形成开口，并且在PMOS区域上形成开口。此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

2. 发明申请

US20150054087A1 REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE 有权
标题翻译：替代CMOS器件的金属门结构
公开(公告)号：US20150054087A1
公开(公告)日：2015-02-26
申请号：US14500914
申请日：2014-09-29
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L27/0922 , H01L21/02697 , H01L21/823842 , H01L21/823857 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.
摘要翻译：一种CMOS器件，其在nFET部分和pFET部分之间包括nFET部分，pFET部分和层间电介质。 nFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，直接物理接触的第二氮化钛层其中阻挡层和填充凹槽的其余部分的栅极金属。 pFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，阻挡层上的第二氮化钛层与第二氮化钛层直接物理接触的第三氮化钛层和填充凹槽的其余部分的栅极金属。

3. 发明授权

US09455203B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US09455203B2
公开(公告)日：2016-09-27
申请号：US14992739
申请日：2016-01-11
申请人： International Business Machines Corporation , Global Foundries Inc
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/02 , H01L29/161 , H01L29/10
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
摘要翻译：其中施加高k电介质的替代金属栅极工艺。高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。可以在高k电介质上形成伪栅极结构，并被蚀刻以在NMOS区域上形成开口，并且在PMOS区域上形成开口。此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

4. 发明授权

US09041118B2 Replacement metal gate structure for CMOS device 有权
标题翻译： CMOS器件替代金属栅极结构
公开(公告)号：US09041118B2
公开(公告)日：2015-05-26
申请号：US14500914
申请日：2014-09-29
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/70 , H01L27/092 , H01L29/49 , H01L29/423
CPC分类号： H01L27/0922 , H01L21/02697 , H01L21/823842 , H01L21/823857 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.
摘要翻译：一种CMOS器件，其在nFET部分和pFET部分之间包括nFET部分，pFET部分和层间电介质。 nFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，直接物理接触的第二氮化钛层其中阻挡层和填充凹槽的其余部分的栅极金属。 pFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，阻挡层上的第二氮化钛层与第二氮化钛层直接物理接触的第三氮化钛层和填充凹槽的其余部分的栅极金属。

5. 发明申请

US20140131809A1 REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE 有权
标题翻译：替代CMOS器件的金属门结构
公开(公告)号：US20140131809A1
公开(公告)日：2014-05-15
申请号：US13676575
申请日：2012-11-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBAL FOUNDRIES INC
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/02 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/02697 , H01L21/823842 , H01L21/823857 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET and pFET portions, resulting in a recess on the nFET portion and a recess on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET and pFET portions; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET and pFET portions; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET and pFET portions; and filling the remainder of the cavity on the nFET and pFET portions with a metal.
摘要翻译：一种制造用于CMOS器件的替代金属栅极结构的方法，包括在CMOS器件的nFET部分和pFET部分上形成伪栅极结构; 在所述虚拟栅极结构之间沉积层间电介质; 从nFET和pFET部分去除伪栅极结构，导致nFET部分上的凹槽和pFET部分上的凹陷; 将栅电介质共形沉积在nFET和pFET部分上的凹槽中; 将第一氮化钛，氮化钽和第二氮化钛的顺序层沉积到nFET和pFET部分上的凹槽中; 仅从nFET部分去除第二层氮化钛; 将第三层氮化钛沉积到nFET和pFET部分上的凹槽中; 并用金属填充nFET和pFET部分上的空腔的其余部分。

6. 发明申请

US20140131808A1 REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE 有权
标题翻译：替代CMOS器件的金属门结构
公开(公告)号：US20140131808A1
公开(公告)日：2014-05-15
申请号：US13676483
申请日：2012-11-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBAL FOUNDRIES INC
发明人： Takashi Ando , Kisik Choi , Srikanth B. Samavedam
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823842 , H01L21/823857
摘要： A method of fabricating a replacement metal gate structure for a CMOS device. The method includes forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess on the nFET portion and a recess on the pFET portion; depositing a first layer of titanium nitride into the recesses on the nFET portion and pFET portion; removing the first layer of titanium nitride from the nFET portion only; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion; depositing a gate metal onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion to fill the remainder of the recesses.
摘要翻译：一种制造用于CMOS器件的替代金属栅极结构的方法。该方法包括在CMOS器件的nFET部分和pFET部分上形成伪栅极结构; 在所述虚拟栅极结构之间沉积层间电介质; 从nFET部分和pFET部分去除伪栅极结构，导致nFET部分上的凹槽和pFET部分上的凹部; 将第一层氮化钛沉积到nFET部分和pFET部分上的凹陷中; 仅从nFET部分去除第一层氮化钛; 将第二层氮化钛沉积到nFET部分和pFET部分上的凹槽中; 在nFET部分和pFET部分上的凹槽中的第二氮化钛层上沉积栅极金属，以填充其余凹部。

7. 发明授权

US08895434B2 Replacement metal gate structure for CMOS device 有权
标题翻译： CMOS器件替代金属栅极结构
公开(公告)号：US08895434B2
公开(公告)日：2014-11-25
申请号：US13676575
申请日：2012-11-14
申请人： International Business Machines Corporation , Global Foundries Inc
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/44 , H01L21/02 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/02697 , H01L21/823842 , H01L21/823857 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A method of fabricating a replacement metal gate structure for a CMOS device including forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET and pFET portions, resulting in a recess on the nFET portion and a recess on the pFET portion; conformally depositing a gate dielectric into the recesses on the nFET and pFET portions; depositing sequential layers of a first titanium nitride, tantalum nitride and a second titanium nitride into the recesses on the nFET and pFET portions; removing the second layer of titanium nitride from the nFET portion only; depositing a third layer of titanium nitride into the recesses on the nFET and pFET portions; and filling the remainder of the cavity on the nFET and pFET portions with a metal.
摘要翻译：一种制造用于CMOS器件的替代金属栅极结构的方法，包括在CMOS器件的nFET部分和pFET部分上形成伪栅极结构; 在所述虚拟栅极结构之间沉积层间电介质; 从nFET和pFET部分去除伪栅极结构，导致nFET部分上的凹槽和pFET部分上的凹陷; 将栅电介质共形沉积在nFET和pFET部分上的凹槽中; 将第一氮化钛，氮化钽和第二氮化钛的顺序层沉积到nFET和pFET部分上的凹槽中; 仅从nFET部分去除第二层氮化钛; 将第三层氮化钛沉积到nFET和pFET部分上的凹槽中; 并用金属填充nFET和pFET部分上的空腔的其余部分。

8. 发明授权

US09263344B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US09263344B2
公开(公告)日：2016-02-16
申请号：US14564603
申请日：2014-12-09
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/02 , H01L29/161
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
摘要翻译：其中施加高k电介质的替代金属栅极工艺。高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。或者，在NMOS和PMOS区域中去除伪栅极以在NMOS和PMOS区域中留下开口之后，可以在沉积在PMOS开口中的NMOS开口或氧化铝中沉积氧化镧。此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

9. 发明申请

US20150311206A1 METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS 有权
标题翻译：用于CMOS应用和结果产品的晶体管器件的门结构的方法
公开(公告)号：US20150311206A1
公开(公告)日：2015-10-29
申请号：US14793005
申请日：2015-07-07
申请人： GLOBAL FOUNDRIES Inc.
发明人： Zhendong Hong , Susie Tzeng , Amol Joshi , Ashish Bodke , Divya Pisharoty , Usha Raghuram , Olov Karlsson , Kisik Choi , Salil Mujumdar , Paul R. Besser , Jinping Liu , Hoon Kim
IPC分类号： H01L27/092 , H01L29/51 , H01L29/49
CPC分类号： H01L27/0922 , H01L21/28097 , H01L21/28185 , H01L21/28194 , H01L21/823835 , H01L27/092 , H01L29/4975 , H01L29/517 , H01L29/66545
摘要： An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.
摘要翻译：集成电路产品包括具有栅极结构的NMOS晶体管，该栅极结构包括NMOS栅绝缘层，位于NMOS栅绝缘层上的第一NMOS金属层，位于第一NMOS金属层上方的NMOS金属硅化物材料，位于NMOS栅极绝缘层上方并与NMOS栅绝缘层接触的第二金属材料，第一NMOS金属层和NMOS金属硅化物层。 PMOS晶体管具有栅极结构，其包括PMOS栅极绝缘层，位于PMOS栅极绝缘层上的第一PMOS金属层，位于第一PMOS金属层上方的PMOS金属硅化物材料和位于第一PMOS金属层上方的第二金属材料层并且与PMOS栅绝缘层，第一PMOS金属层和PMOS金属硅化物层接触。

10. 发明申请

US20150147876A1 LOW THRESHOLD VOLTAGE CMOS DEVICE 有权
标题翻译：低电压电压CMOS器件
公开(公告)号：US20150147876A1
公开(公告)日：2015-05-28
申请号：US14564603
申请日：2014-12-09
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc.
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/161 , H01L29/51 , H01L21/02 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
摘要翻译：其中施加高k电介质的替代金属栅极工艺。高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。或者，在NMOS和PMOS区域中去除伪栅极以在NMOS和PMOS区域中留下开口之后，可以在沉积在PMOS开口中的NMOS开口或氧化铝中沉积氧化镧。此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式