专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070234009A1 Processor having a dedicated hash unit integrated within 失效
标题翻译：具有集成在其中的专用散列单元的处理器
公开(公告)号：US20070234009A1
公开(公告)日：2007-10-04
申请号：US11758892
申请日：2007-06-06
申请人： GILBERT WOLRICH , Matthew Adiletta , William Wheeler
发明人： GILBERT WOLRICH , Matthew Adiletta , William Wheeler
IPC分类号： G06F9/40
CPC分类号： G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。还公开了基于执行上下文的切换和分支的指令。

2. 发明申请

US20060069882A1 Memory controller for processor having multiple programmable units 有权
标题翻译：具有多个可编程单元的处理器的存储器控制器
公开(公告)号：US20060069882A1
公开(公告)日：2006-03-30
申请号：US11232566
申请日：2005-09-21
申请人： William Wheeler , Bradley Burres , Matthew Adiletta , Gilbert Wolrich
发明人： William Wheeler , Bradley Burres , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F13/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。所述处理器还包括存储器控制系统，所述存储器控制系统具有第一存储器控制器，所述第一存储器控制器基于所述存储器引用是针对偶数存储体还是存储器的奇数存储器排序存储器引用;以及第二存储器控制器，内存引用是读取引用或写入引用。

3. 发明授权

US07620702B1 Providing real-time control data for a network processor 失效
标题翻译：为网络处理器提供实时控制数据
公开(公告)号：US07620702B1
公开(公告)日：2009-11-17
申请号：US09473571
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta , William Wheeler
IPC分类号： G06F15/177
CPC分类号： G06F15/17
摘要： A multiprocessor includes a module configured to collect status data, one or more processing engines, and a push engine. Part of the status data is collected from devices connected to a bus and indicates readiness of the devices to participate in data transfers over the bus. The processing engines schedule transfers of data packets between the processor and the devices. The push engine performs unsolicited transfers of a portion of the status data to the processing engines in response to the module collecting new status data.
摘要翻译：多处理器包括被配置为收集状态数据的模块，一个或多个处理引擎和推动引擎。状态数据的一部分从连接到总线的设备收集，并指示设备参与通过总线进行数据传输的准备状态。处理引擎在处理器和设备之间调度数据包的传输。响应于模块收集新的状态数据，推送引擎执行状态数据的一部分的未经请求的转移到处理引擎。

4. 发明授权

US06577542B2 Scratchpad memory 有权
公开(公告)号：US06577542B2
公开(公告)日：2003-06-10
申请号：US10010334
申请日：2001-10-22
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

5. 发明申请

US20060090039A1 Method and apparatus to enable DRAM to support low-latency access via vertical caching 失效
标题翻译：使DRAM能够通过垂直高速缓存支持低延迟访问的方法和装置
公开(公告)号：US20060090039A1
公开(公告)日：2006-04-27
申请号：US10974122
申请日：2004-10-27
申请人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
发明人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： H04L12/2854 , G06F12/0862 , G06F12/0875
摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.
摘要翻译：实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。在一个实施例中，DRAM包括双数据速率（DDR）DRAM。公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。该架构还包括用于执行各种分组处理功能的多个计算引擎。一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。随后，一个或多个分组处理功能可以通过从高速缓存访问功能元数据来操作。功能完成后，将功能元数据写回到基于DRAM的商店。该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

6. 发明授权

US06307789B1 Scratchpad memory 有权
标题翻译：便条记忆
公开(公告)号：US06307789B1
公开(公告)日：2001-10-23
申请号：US09473111
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.
摘要翻译：集成电路包括随机存取存储器（RAM）存储器和位于一个半导体芯片上的控制器。控制器被耦合以从RAM存储器读取数据并向RAM存储器写入数据。控制器可编程为对存储在RAM中的数据字执行按位运算。

7. 发明申请

US20060156303A1 Multi-threaded sequenced receive for fast network port stream of packets 有权
标题翻译：多线程排序接收快速网络端口流数据包
公开(公告)号：US20060156303A1
公开(公告)日：2006-07-13
申请号：US11239547
申请日：2005-09-28
申请人： Donald Hooper , Matthew Adiletta , Gilbert Wolrich
发明人： Donald Hooper , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/3851 , G06F9/3885 , G06F9/485 , G06F9/4881 , G06F9/544
摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.
摘要翻译：一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。

8. 发明申请

US20050216710A1 Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section 有权
公开(公告)号：US20050216710A1
公开(公告)日：2005-09-29
申请号：US11092366
申请日：2005-03-29
申请人： Hugh Wilkinson , Matthew Adiletta , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein , Myles Wilde
发明人： Hugh Wilkinson , Matthew Adiletta , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein , Myles Wilde
IPC分类号： G06F15/78 , G06F9/30
CPC分类号： G06F15/8053
摘要： A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

9. 发明申请

US20050149665A1 Scratchpad memory 审中-公开
公开(公告)号：US20050149665A1
公开(公告)日：2005-07-07
申请号：US11058855
申请日：2005-02-16
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
IPC分类号： G11C7/10 , G06F13/00
CPC分类号： G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

10. 发明授权

US06876561B2 Scratchpad memory 失效
标题翻译：便条记忆
公开(公告)号：US06876561B2
公开(公告)日：2005-04-05
申请号：US10726757
申请日：2003-12-03
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.
摘要翻译：集成电路包括随机存取存储器（RAM）存储器和位于一个半导体芯片上的控制器。控制器被耦合以从RAM存储器读取数据并向RAM存储器写入数据。控制器可编程为对存储在RAM中的数据字执行按位运算。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式