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1. 发明申请

US20110202796A1 MICROPROCESSOR WITH SYSTEM-ROBUST SELF-RESET CAPABILITY 有权
标题翻译：具有系统稳定自复位能力的微处理器
公开(公告)号：US20110202796A1
公开(公告)日：2011-08-18
申请号：US12944269
申请日：2010-11-11
申请人： G. Glenn Henry , Darius D. Gaskins , Jason Chen
发明人： G. Glenn Henry , Darius D. Gaskins , Jason Chen
IPC分类号： G06F11/00 , G06F13/28 , G06F13/24
CPC分类号： G06F11/3648
摘要： A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.
摘要翻译：微处理器包括总线接口单元，该总线接口单元将微处理器连接到总线，总线包括一个信号，当被断言时，它指示所有总线代理人不要发起总线事务。微代码使得总线接口单元响应于检测到事件而声明信号并复位微处理器，但不会重置总线接口单元的断言总线上的信号的部分。复位后，微码使总线接口单元解除总线上的信号。此外，微代码设置一个标志，并在复位本身之前将微处理器状态保存到存储器中，但不会将中断控制器复位。复位后，微码从存储器重新加载微处理器的状态。然而，如果微码确定标志被设置，它将放弃重新加载中断控制器的状态。

2. 发明授权

US08370684B2 Microprocessor with system-robust self-reset capability 有权
标题翻译：具有系统稳定自复位能力的微处理器
公开(公告)号：US08370684B2
公开(公告)日：2013-02-05
申请号：US12944269
申请日：2010-11-11
申请人： G. Glenn Henry , Darius D. Gaskins , Jason Chen
发明人： G. Glenn Henry , Darius D. Gaskins , Jason Chen
IPC分类号： G06F11/26
CPC分类号： G06F11/3648
摘要： A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.
摘要翻译：微处理器包括总线接口单元，该总线接口单元将微处理器连接到总线，总线包括一个信号，当被断言时，它指示所有总线代理人不要发起总线事务。微代码使得总线接口单元响应于检测到事件而声明信号并复位微处理器，但不会重置总线接口单元的断言总线上的信号的部分。复位后，微码使总线接口单元解除总线上的信号。此外，微代码设置一个标志，并在复位本身之前将微处理器状态保存到存储器中，但不会将中断控制器复位。复位后，微码从存储器重新加载微处理器的状态。然而，如果微码确定标志被设置，它将放弃重新加载中断控制器的状态。

3. 发明申请

US20110185160A1 MULTI-CORE PROCESSOR WITH EXTERNAL INSTRUCTION EXECUTION RATE HEARTBEAT 有权
标题翻译：具有外部指令执行速率心脏的多核心处理器
公开(公告)号：US20110185160A1
公开(公告)日：2011-07-28
申请号：US12964949
申请日：2010-12-10
申请人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
发明人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F1/14 , G06F13/28
CPC分类号： G06F11/364 , G06F11/3652 , G06F11/3656
摘要： A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.
摘要翻译：一种用于调试多核微处理器的方法包括使微处理器执行指令的实际执行，并从微处理器获得心跳信息，该信号指定多个核心相对于彼此的指令的实际执行顺序，命令相应的多个的核心的软件功能模型的实例，以根据由心跳信息指定的实际执行顺序来执行指令，以生成指令执行的模拟结果，并将模拟结果与指令执行的实际结果进行比较以确定它们是否匹配。每个核心输出指示执行指示符，指示核心每个核心时钟执行的指令数。心跳发生器为外部总线上的每个内核生成一个心跳指示符，指示每个外部总线时钟周期内由每个内核执行的指令数。

4. 发明授权

US08762779B2 Multi-core processor with external instruction execution rate heartbeat 有权
标题翻译：具有外部指令执行率心跳的多核处理器
公开(公告)号：US08762779B2
公开(公告)日：2014-06-24
申请号：US12964949
申请日：2010-12-10
申请人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
发明人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/364 , G06F11/3652 , G06F11/3656
摘要： A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.
摘要翻译：一种用于调试多核微处理器的方法包括使微处理器执行指令的实际执行，并从微处理器获得心跳信息，该信号指定多个核心相对于彼此的指令的实际执行顺序，命令相应的多个的核心的软件功能模型的实例，以根据由心跳信息指定的实际执行顺序来执行指令，以生成指令执行的模拟结果，并将模拟结果与指令执行的实际结果进行比较以确定它们是否匹配。每个核心输出指示执行指示符，指示核心每个核心时钟执行的指令数。心跳发生器为外部总线上的每个内核生成一个心跳指示符，指示每个外部总线时钟周期内由每个内核执行的指令数。

5. 发明授权

US08639919B2 Tracer configuration and enablement by reset microcode 有权
标题翻译：示踪器配置和启用复位微码
公开(公告)号：US08639919B2
公开(公告)日：2014-01-28
申请号：US13293268
申请日：2011-11-10
申请人： G. Glenn Henry , Jason Chen
发明人： G. Glenn Henry , Jason Chen
IPC分类号： G06F9/00 , G06F9/24 , G06F9/44 , G06F15/177
CPC分类号： G06F11/36
摘要： A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a debug mode, the reset microcode configures and enables the microprocessor's debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a normal mode, the reset microcode refrains from configuring and enabling the microprocessor's debug logic. The reset logic flag is indicated by an alterable fuse or a debugger-programmable scan register. Debug configuration initialization values are also provided by several alternative structures, including the reset microcode itself, alterable fuses, and debugger-programmable scan registers. Corresponding methods are also provided for configuring the debug logic of a microprocessor.
摘要翻译：微处理器被提供有复位逻辑标志和相应的复位微代码，其在微处理器随后提取和执行用户指令之前选择性地启用复位微代码来设置和使能调试逻辑。当复位逻辑标志被设置为调试模式时，复位微码在微处理器随后提取和执行用户指令之前配置并启用微处理器的调试逻辑。当复位逻辑标志设置为正常模式时，复位微代码不会配置和启用微处理器的调试逻辑。复位逻辑标志由可变保险丝或调试器可编程扫描寄存器指示。调试配置初始化值也由几种替代结构提供，包括复位微码本身，可变保险丝和调试器可编程扫描寄存器。还提供了相应的方法来配置微处理器的调试逻辑。

6. 发明申请

US20120185681A1 TRACER CONFIGURATION AND ENABLEMENT BY RESET MICROCODE 有权
标题翻译：跟踪器配置和复位微控制器
公开(公告)号：US20120185681A1
公开(公告)日：2012-07-19
申请号：US13293268
申请日：2011-11-10
申请人： G. Glenn Henry , Jason Chen
发明人： G. Glenn Henry , Jason Chen
IPC分类号： G06F9/00 , G06F1/24
CPC分类号： G06F11/36
摘要： A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a debug mode, the reset microcode configures and enables the microprocessor's debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a normal mode, the reset microcode refrains from configuring and enabling the microprocessor's debug logic. The reset logic flag is indicated by an alterable fuse or a debugger-programmable scan register. Debug configuration initialization values are also provided by several alternative structures, including the reset microcode itself, alterable fuses, and debugger-programmable scan registers. Corresponding methods are also provided for configuring the debug logic of a microprocessor.
摘要翻译：微处理器被提供有复位逻辑标志和相应的复位微代码，其在微处理器随后提取和执行用户指令之前选择性地启用复位微代码来设置和使能调试逻辑。当复位逻辑标志被设置为调试模式时，复位微码在微处理器随后提取和执行用户指令之前配置并启用微处理器的调试逻辑。当复位逻辑标志设置为正常模式时，复位微代码不会配置和启用微处理器的调试逻辑。复位逻辑标志由可变保险丝或调试器可编程扫描寄存器指示。调试配置初始化值也由几种替代结构提供，包括复位微码本身，可变保险丝和调试器可编程扫描寄存器。还提供了相应的方法来配置微处理器的调试逻辑。

7. 发明申请

US20210088894A1 GLASS-FREE 3D DISPLAY SYSTEM USING DUAL IMAGE PROJECTION AND TRI-COLORS GRATING MULTIPLEXING PANELS 有权
公开(公告)号：US20210088894A1
公开(公告)日：2021-03-25
申请号：US17117020
申请日：2020-12-09
申请人： Duan-Jun Chen , Jason Chen
发明人： Duan-Jun Chen , Jason Chen
IPC分类号： G03B35/22 , G02B30/26 , G03B21/60
摘要： The problem of 3D panel display systems either (a) requiring special glasses to separate left and right viewing images, or (b) having auto-stereoscopic 3D with compromised fidelity, is solved by providing a projection three dimensional (3D) display system for providing glass-free, 3D display to a plurality of viewing volumetric pairs (VVAs) in space corresponding to a hypothetical plurality of viewers' eye aperture pairs, the projection 3D display system comprising: (a) a dual-image projector configured to project both a left viewing tri-color image and a right viewing tri-color image; and (b) means for (1) receiving a tri-color mixed input beam encompassing the left and right viewing tri-color images, (2) multiplying the tri-color mixed input beam into a plurality of tri-color mixed output beams, and (3) focusing the plurality of tri-color mixed beams for viewing at the VVAs.

8. 外观设计

USD698568S1 Media stand 有权
公开(公告)号：USD698568S1
公开(公告)日：2014-02-04
申请号：US29459283
申请日：2013-06-27
申请人： Jason Chen
设计人： Jason Chen

9. 外观设计

USD664528S1 Mobile phone stand 有权
标题翻译：手机支架
公开(公告)号：USD664528S1
公开(公告)日：2012-07-31
申请号：US29399028
申请日：2011-08-09
申请人： Jason Chen , Yong-Yue Cai
设计人： Jason Chen , Yong-Yue Cai

10. 发明授权

US07661967B2 Retractable memory drive 有权
标题翻译：伸缩式记忆体驱动
公开(公告)号：US07661967B2
公开(公告)日：2010-02-16
申请号：US12205620
申请日：2008-09-05
申请人： Choon Tak Tang , Jason Chen , Kevin Tseng
发明人： Choon Tak Tang , Jason Chen , Kevin Tseng
IPC分类号： H01R13/60 , H01R13/44
CPC分类号： H01R13/6658
摘要： A retractable memory drive in accordance with the present invention comprises a top casing, a middle carrier, an electronic device such as a USB thumb drive, and a bottom casing. A positioning device on the middle carrier has a portion that protrudes outside the casing and operates like a button. The location of the positioning device where the button is located has two key attributes. First, there is a protrusion that acts as a lock with the casing. Second, the area below the button is not rigid and so it gives way when pressure is applied to the button. The top and bottom casings provide a casing structure which includes two detents. One detent is for locking the device with the connector in the extended position, and one detent for locking the device with the connector retracted in the in position. This allows for just one press of the extended portion of the positioning device to unlock it from its present position. When the device reaches its new position it will automatically lock. There are also guide rails that allow the middle carrier to remain in an appropriate position.
摘要翻译：根据本发明的可伸缩存储器驱动器包括顶壳，中间托架，诸如USB拇指驱动器的电子装置和底壳。中间托架上的定位装置具有突出到壳体外部并像按钮一样操作的部分。按钮所在的定位装置的位置具有两个关键属性。首先，有一个凸起，其作为与壳体的锁定。第二，按钮下面的区域不是刚性的，所以当压力施加到按钮时，它会让位。顶部和底部壳体提供包括两个棘爪的套管结构。一个制动器用于将连接器的装置锁定在延伸位置，并且一个棘爪用于将装置锁定在连接器的位置。这允许仅定位装置的延伸部分的一次按压将其从其当前位置解锁。当设备达到新位置时，它将自动锁定。还有导轨允许中间托架保持在适当的位置。

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