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1. 发明授权

US06412048B1 Traffic controller using priority and burst control for reducing access latency 有权
标题翻译：流量控制器使用优先级和突发控制来减少访问延迟
公开(公告)号：US06412048B1
公开(公告)日：2002-06-25
申请号：US09189080
申请日：1998-11-09
申请人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
发明人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
IPC分类号： G06F1200
CPC分类号： G06F13/28
摘要： A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.
摘要翻译：一种响应于多个请求访问存储器的存储器业务访问控制器（18）。所述控制器包括电路（18d），用于为所述多个请求中的每一个分配与所述请求对应的初始优先级值。控制器还包括用于将多个请求中的所选择的请求的初始优先级值改变为不同的优先级值的电路（18b，18d，18e，18f）。最后，控制器包括用于响应于具有最高优先级值的多个请求中的请求而输出（18d）信号以使存储器访问的电路。

2. 发明授权

US06253297B1 Memory control using memory state information for reducing access latency 有权
标题翻译：内存控制使用内存状态信息来减少访问延迟
公开(公告)号：US06253297B1
公开(公告)日：2001-06-26
申请号：US09170834
申请日：1998-10-13
申请人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
发明人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
IPC分类号： G06F1200
CPC分类号： G06F13/28
摘要： A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative of requests to access the memory. Given these signals, a first such signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory, and a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory. The memory controller circuit also includes determining circuitry (30, RAn, AC13 Bn13 ROW, C_B_Rn) for determining whether the second address is directed to a same one of the plurality of rows as the first address. Still further, the memory controller circuit includes circuitry (30) for issuing control signals to the memory in response to receiving signals representative of requests to access the memory. These control signals cause a first memory access to occur in response to the first request and a second memory access to occur in response to the second request. Lastly, in response to the determining circuitry determining that the second address is directed to the same one of the plurality of rows as the first address, the circuitry for issuing control signals issues control signals to the memory such that the same one of the plurality of rows is maintained active between the first and second access.
摘要翻译：一种用于耦合到存储器（24）的存储器控制器电路（18a），其中存储器具有多个行。存储器控制器电路包括用于接收表示访问存储器的请求的信号的电路（28）。给定这些信号，表示访问存储器的第一请求的第一信号由用于接收的电路接收并且包括存储器中的第一地址，并且表示访问存储器的第二请求的第二信号由用于在第一信号之后接收并包括存储器中的第二地址的电路。存储器控制器电路还包括用于确定第二地址是否被引导到与第一地址相同的多行中的确定电路（30，RAn，AC13Bn13ROW，C_B_Rn）。此外，存储器控制器电路包括用于响应于代表访问存储器的请求的接收信号向存储器发出控制信号的电路（30）。这些控制信号导致响应于第一请求而发生第一存储器访问，并且响应于第二请求而发生第二存储器访问。最后，响应于确定电路确定第二地址指向与第一地址相同的多行行，用于发出控制信号的电路向存储器发出控制信号，使得多个行在第一和第二访问之间保持活动。

3. 发明授权

US06430664B1 Digital signal processor with direct and virtual addressing 有权
标题翻译：具有直接和虚拟寻址功能的数字信号处理器
公开(公告)号：US06430664B1
公开(公告)日：2002-08-06
申请号：US09434606
申请日：1999-11-05
申请人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
发明人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： A DSP (10) accesses internal memory using physical addresses and has a internal MMU (19) which allows the DSP (10) to work with a large virtual address space mapped to an external memory (20). The MMU (19) performs the translation between a virtual address and the physical address associated with the external memory (20). The MMU (19) includes a translation lookaside buffer (28) and walking table logic (32) for translating virtual addresses to physical addresses.
摘要翻译： DSP（10）使用物理地址访问内部存储器并且具有内部MMU（19），其允许DSP（10）处理映射到外部存储器（20）的大的虚拟地址空间。 MMU（19）执行虚拟地址与与外部存储器（20）相关联的物理地址之间的转换。 MMU（19）包括翻译后备缓冲器（28）和用于将虚拟地址转换为物理地址的步行表逻辑（32）。

4. 发明授权

US06321299B1 Computer circuits, systems, and methods using partial cache cleaning 有权
标题翻译：使用部分缓存清理的计算机电路，系统和方法
公开(公告)号：US06321299B1
公开(公告)日：2001-11-20
申请号：US09187118
申请日：1998-11-05
申请人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
发明人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , Y02D10/13
摘要： A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data (64) to the cache memory at a location corresponding to each of the plurality of write addresses. Second, the method cleans (70) a selected number (68) of lines in the cache memory. For each of the selected number of lines, the cleaning step evaluates a dirty indicator corresponding to data in the line and copies data from the line to another memory if the dirty indicator indicates the data in the line is dirty. Lastly, the selected number of lines which are cleaned is less than the predetermined number of cache lines.
摘要翻译：一种操作计算系统（10）的方法（50）。计算系统包括高速缓冲存储器（12b），高速缓冲存储器具有预定数量的高速缓存行。首先，对于多个写入地址，该方法在与多个写入地址中的每一个相对应的位置向高速缓冲存储器写入数据（64）。第二，该方法清除（70）高速缓冲存储器中选定数量（68）行。对于选定数量的行中的每一行，如果脏指示器指示行中的数据变脏，则清洁步骤将评估与行中的数据相对应的脏指示器，并将数据从行复制到另一个存储器。最后，被清理的所选择的行数小于预定数量的高速缓存行。

5. 发明授权

US06934820B2 Traffic controller using priority and burst control for reducing access latency 有权
标题翻译：流量控制器使用优先级和突发控制来减少访问延迟
公开(公告)号：US06934820B2
公开(公告)日：2005-08-23
申请号：US10166160
申请日：2002-06-10
申请人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
发明人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
IPC分类号： G06F12/00 , G06F13/28 , G06F13/30
CPC分类号： G06F13/28
摘要： A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.
摘要翻译：一种响应于多个请求访问存储器的存储器业务访问控制器（18）。所述控制器包括电路（18d），用于针对所述多个请求中的每一个将与所述请求对应的初始优先级值相关联。控制器还包括用于将多个请求中的所选择的请求的初始优先级值改变为不同的优先级值的电路（18b，18d，18e，18f）。最后，控制器包括用于输出（18d）响应于具有最高优先级值的多个请求中的请求而使存储器访问的信号的电路。

6. 发明授权

US07840784B2 Test and skip processor instruction having at least one register operand 有权
标题翻译：测试和跳过具有至少一个寄存器操作数的处理器指令
公开(公告)号：US07840784B2
公开(公告)日：2010-11-23
申请号：US10632084
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F9/32
CPC分类号： G06F9/30069 , G06F9/30181 , G06F9/30185 , G06F9/30189 , G06F9/30196 , G06F9/355 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is “skipped.” The test and skip instruction may specify that the operands used in the comparison include (1) the contents of two registers, (2) the contents of one register and the contents of a memory location, or (3) the contents of one register and a stack value. In the second mode (an operand being from memory), a register is specified in the test and skip instruction that contains a value from which a pointer may be calculated. The calculated pointer preferably points to the memory location. If a stack value is used in the execution of the test and skip instruction, the instruction may include a reference to a register that points to the top of the stack. Further, the stack pointer may be adjusted automatically if the stack is used to provide an operand for the instruction. Embodiments may include apparatus and methods.
摘要翻译：处理器可以执行包括或以其他方式指定在比较操作中使用的至少两个操作数的测试和跳过指令。根据比较结果，测试和跳过指令之后的指令被“跳过”。测试和跳过指令可以指定比较中使用的操作数包括（1）两个寄存器的内容，（2）一个寄存器的内容和存储器位置的内容，或（3）一个寄存器的内容和堆栈值。在第二模式（一个来自存储器的操作数）中，在测试和跳过指令中指定一个寄存器，该指令包含可以计算指针的值。计算出的指针最好指向存储器位置。如果在执行测试和跳过指令时使用堆栈值，则该指令可以包括对指向堆栈顶部的寄存器的引用。此外，如果堆栈用于为指令提供操作数，则可以自动调整堆栈指针。实施例可以包括装置和方法。

7. 发明授权

US07058765B2 Processor with a split stack 有权
标题翻译：处理器与分离堆栈
公开(公告)号：US07058765B2
公开(公告)日：2006-06-06
申请号：US10632079
申请日：2003-07-31
申请人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
IPC分类号： G06F12/08
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/3012 , G06F9/30174 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/1036 , G06F12/126 , G06F2212/502 , G06F2212/681 , Y02D10/13
摘要： Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas that are external to the core of the processor. Operands are preferably provided to an arithmetic logic unit (ALU) by the micro-stack, and in the case of underflow (micro-stack empty), operands may be fetched from the main stack. Operands are written to the main stack during overflow (micro-stack full) or by explicit flushing of the micro-stack. By optimizing the size of the micro-stack, the number of operands fetched from the main stack may be reduced, and consequently the processor's power consumption may be reduced.
摘要翻译：公开了用于实现具有分组堆栈的处理器的方法和装置。在一些实施例中，处理器包括主堆栈和微堆栈。微堆优选地实现在处理器的核心中，而主堆栈可以在处理器核心外部的区域中实现。操作数优选地通过微栈提供给算术逻辑单元（ALU），并且在下溢（微堆空）的情况下，可以从主堆栈获取操作数。在溢出（微型堆栈完整）或通过显式冲洗微型堆栈时，操作数将写入主堆栈。通过优化微堆栈的大小，可以减少从主堆栈取出的操作数的数量，从而可以降低处理器的功耗。

8. 发明授权

US06772326B2 Interruptible an re-entrant cache clean range instruction 有权
标题翻译：中断缓存清除范围指令
公开(公告)号：US06772326B2
公开(公告)日：2004-08-03
申请号：US10157576
申请日：2002-05-29
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F944
CPC分类号： G06F9/4843 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F12/0842 , G06F12/0891
摘要： A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance with a program counter. If an interrupt (804) is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch (810), the interrupt is serviced (820). Upon returning from the interrupt service routine (830, 834), execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register. If different, execution of the clean instruction is restarted by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. In this manner, no additional context information needs to be saved during a context switch in order to allow the clean instruction to be interruptible. If the interrupt occurred during a non-interruptible instruction, then the instruction is completed before the context switch and a return (830, 832) after the interrupt service routine begins execution at the next instruction (803). Other instructions that perform a sequence of operations can also be made interruptible in a similar manner.
摘要翻译：提供了一种数字系统和操作方法，其中提供了一种用于清洁由起始参数和结束参数指定的存储区域中的地址范围的方法。根据程序计数器，可以以指令序列（800）执行中断清除指令（802）。如果在执行干净指令期间接收到中断（804），干净指令的执行将在完成之前暂停。执行上下文切换（810）后，中断服务（820）。在从中断服务程序（830,834）返回时，通过将清除指令提供的开始参数和结束参数与执行期间使用的相应起始寄存器和结束寄存器的当前内容进行比较来恢复干净指令的执行干净的说明。如果相同，则使用起始寄存器和结束寄存器的当前内容恢复干净指令的执行。如果不同，通过将清除指令提供的启动参数存储在起始寄存器中并通过将结束参数存储在结束寄存器中来重新启动干净指令的执行。以这种方式，在上下文切换期间不需要保存附加上下文信息，以便允许清除指令是可中断的。如果在不可中断指令期间发生中断，则在中断服务程序在下一条指令（803）开始执行之前，上下文切换和返回（830,832）之前完成指令。执行一系列操作的其他指令也可以以类似的方式中断。

9. 发明授权

US06760829B2 MMU descriptor having big/little endian bit to control the transfer data between devices 有权
标题翻译： MMU描述符具有大/小端位以控制设备之间的传输数据
公开(公告)号：US06760829B2
公开(公告)日：2004-07-06
申请号：US09932807
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel , Dominique D'Inverno
发明人： Serge Lasserre , Gerard Chauvel , Dominique D'Inverno
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory management unit (MMU) (500-510) and an endianism attribute bit is defined for each region. For each memory request to the memory, the endianism attribute bit for the selected region is provided by the MMU. Each memory transaction request is completed in accordance with the endianism attribute of the selected region. Depending on the capability of a given initiator resource, the memory request address is adjusted to agree with the endianism attribute of the selected region, or an access fault is generated (530) if the endianism of the initiating resource does not match the endianism attribute of the selected memory region. A resource identification value (R-ID) provided by each of the initiator resources is used to identify the endianism of each of the initiator resources.
摘要翻译：数字系统具有由几个发起者资源（540-550）共享的存储器（506），其中一部分发起者资源是大端，另一部分发起者资源是小端。存储器通过存储器管理单元（MMU）（500-510）分离成一组区域，并且为每个区域定义一个endianistic属性位。对于存储器的每个存储器请求，MMU提供所选区域的endianistic属性位。每个存储器事务请求都是根据所选区域的endianism属性完成的。根据给定的启动器资源的能力，调整存储器请求地址以与所选区域的endianism属性一致，或者如果启动资源的endianism不匹配于endianism属性，则生成访问故障（530）所选存储区域。由每个启动器资源提供的资源标识值（R-ID）用于识别每个发起者资源的端点。

10. 发明授权

US06754781B2 Cache with DMA and dirty bits 有权
标题翻译：缓存与DMA和脏位
公开(公告)号：US06754781B2
公开(公告)日：2004-06-22
申请号：US09932643
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0804 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Dirty bit circuitry (DI) is connected to the memory circuit for indicating if data within the cache is incoherent with a secondary back-up memory. DMA circuitry can transfer (1652) blocks of data/instructions (1660) between the cache and a secondary memory (1602). A transfer mode circuit (1681) controls how DMA operations are affected by the dirty bits. If the transfer mode circuit is in a first mode, a DMA operation transfers only segments (1661) indicated as dirty (1685). If the transfer mode circuit is in a second mode, a DMA operation transfers and entire block of data (1660) without regard to dirty indicators (1686). DMA transfers from the cache to secondary memory are thereby configured to be responsive to the dirty bits. A dirty bit mode circuit (1680) controls how DMA transfers affect the dirty bits. When the mode circuit is in a first mode, DMA transfers set the affected dirty bits to a clean state. When the dirty bit mode circuitry is in an alternate mode, DMA transfers set the affected dirty bits to a dirty state. A cache clean operation will thus copy data provided by a DMA transfer and indicated as dirty into backup secondary memory.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以指示多个段的每个段是否保存有效数据，脏位电路（DI）连接到存储器电路，用于指示高速缓存内的数据是否与辅助备份存储器不相干，DMA电路可以传输（1652）块传输模式电路（1681）控制DMA操作如何受脏位的影响，如果传输模式电路处于第一模式，DMA操作（1660）只传输指示为脏的段（1661）（1685），如果传输模式电路处于第二模式，则DMA操作传输和整个数据块（1660），而不考虑脏指示器（1686）。到二级记忆从而被配置为响应于脏位。脏位模式电路（1680）控制DMA传输如何影响脏位。当模式电路处于第一模式时，DMA将受影响的脏位设置为干净状态。当脏位模式电路处于交替模式时，DMA传送将受影响的脏位设置为脏状态。因此，高速缓存清理操作将复制由DMA传输提供的数据，并将其标记为脏到备用辅助存储器中。

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