专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5895951A MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches 失效
标题翻译：通过掺杂沟槽形成深而窄的掺杂区域来实现MOSFET结构和制造工艺
公开(公告)号：US5895951A
公开(公告)日：1999-04-20
申请号：US628493
申请日：1996-04-05
申请人： Koon Chong So , Yan Man Tsui , Fwu-Iuan Hshieh , True-Lon Lin , Danny Chi Nim
发明人： Koon Chong So , Yan Man Tsui , Fwu-Iuan Hshieh , True-Lon Lin , Danny Chi Nim
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/0696 , H01L29/0847
摘要： This invention discloses a MOSFET device which includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough. Each of the vertical cells is surrounded by a polysilicon layer acting as a gate for controlling the source-to-drain current through the channel. The MOSFET device further include a plurality of doping trenches filled with trench-filling materials, The MOSFET device further includes a plurality of deep-doped regions disposed underneath the doping trenches wherein the deep-doped region extends downwardly to a depth which is substantially a sum of an implant depth of the deep-doped region and a vertical diffusion depth below a bottom of the doping trenches.
摘要翻译：本发明公开了一种MOSFET器件，其包括多个垂直单元，每个垂直单元包括源极，漏极和用于通过其传导源极 - 漏极电流的沟道。每个垂直单元被用作控制通过通道的源极 - 漏极电流的栅极的多晶硅层包围。 MOSFET器件还包括填充有沟槽填充材料的多个掺杂沟槽。MOSFET器件还包括设置在掺杂沟槽下方的多个深掺杂区域，其中深掺杂区域向下延伸到基本上为总和的深度的深掺杂区域的注入深度和在掺杂沟槽的底部下方的垂直扩散深度。

2. 发明授权

US5883416A Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage 失效
标题翻译：栅极接触结构，防止接触金属穿过栅极层而不影响击穿电压
公开(公告)号：US5883416A
公开(公告)日：1999-03-16
申请号：US792226
申请日：1997-01-31
申请人： True-Lon Lin , Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
发明人： True-Lon Lin , Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L23/485 , H01L23/48
CPC分类号： H01L29/42368 , H01L29/7811 , H01L29/0696 , H01L29/42372 , H01L29/4238 , H01L2924/0002
摘要： The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.
摘要翻译：本发明公开了一种设置在基板上的功率晶体管。功率器件包括核心单元区域，其包括多个功率晶体管单元，每个功率晶体管单元具有漏极和源极。每个功率晶体管单元还具有形成在衬底上的多晶硅栅极，作为覆盖衬底的多晶硅栅极层的一部分。多晶硅栅极层包括延伸到栅极接触区域的多个多晶栅极层延伸部分，用于与设置在其上的接触金属形成栅极接触。功率晶体管还包括多个耐接触金属焊盘，每个包括设置在多晶栅极层延伸下方的栅极接触区下方的厚氧化物焊盘，由此接触金属电阻焊盘抵抗接触金属穿透其中并且短于底物置于其下。

3. 发明授权

US5877529A Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness 失效
标题翻译： Mosfet终端设计和核心单元配置，以增加击穿电压并提高器件的耐用性
公开(公告)号：US5877529A
公开(公告)日：1999-03-02
申请号：US978667
申请日：1997-11-26
申请人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
发明人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/76 , H01L23/58 , H01L29/94
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/7811 , H01L29/0696 , H01L2924/0002
摘要： Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve higher breakdown voltage and improved device ruggedness. The power transistor includes a core cell area which includes a plurality of power transistor cells and a termination area. The power transistor further includes an outer pickup guarding ring, disposed in the termination area guarding the core cell area, for picking up free charged-particles generated in the termination area for preventing the free charged particles from entering the core cell area. In another preferred embodiment, the power transistor further includes an inner pickup guarding fence and blocks, disposed between the termination area and the core cell area for picking up free charged-particles not yet picked up by the outer pickup guarding ring for preventing the free charged particles from entering the core cell area.
摘要翻译：在本发明中公开了改进的功率MOSFET结构和制造工艺，以实现更高的击穿电压和改进的器件耐用性。功率晶体管包括包含多个功率晶体管单元和端接区域的核心单元区域。功率晶体管还包括外部拾波器保护环，设置在保护核心单元区域的端接区域中，用于拾取终止区域中产生的免费带电粒子，以防止自由带电粒子进入核心单元区域。在另一个优选实施例中，功率晶体管还包括内部拾取器防护栅栏和块，其设置在终端区域和核心单元区域之间，用于拾取由外部拾音器保护环尚未拾取的免费带电粒子，以防止自由充电颗粒进入核心区域。

4. 发明授权

US5986304A Punch-through prevention in trenched DMOS with poly-silicon layer covering trench corners 失效
标题翻译：在沟槽DMOS中进行穿透防止，多晶硅层覆盖沟槽角
公开(公告)号：US5986304A
公开(公告)日：1999-11-16
申请号：US782368
申请日：1997-01-13
申请人： Fwu-Iuan Hshieh , Koon Chong So , True-Lon Lin
发明人： Fwu-Iuan Hshieh , Koon Chong So , True-Lon Lin
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/4238
摘要： The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region. The conductive material filling the trenches including punch-through suppressing blocks covering corners of the cell defined by the intersecting trenches wherein the source region disposed underneath the corners immediately next to the trenches having a lower net concentration of impurities of the first conductivity type than remaining portion of the source region.
摘要翻译：本发明包括具有第一导电类型的衬底，其顶表面包括设置在其中的至少两个相交的沟槽，其中衬有沟槽的绝缘层和填充沟槽的导电材料。晶体管还包括第一导电类型的源极区域，从邻近沟槽的衬底的顶表面朝向衬底延伸。晶体管还具有与第一导电类型相反极性的第二导电类型的主体区域，主体区域从与沟槽相邻的顶表面延伸到衬底并围绕源极区域。填充沟槽的导电材料包括覆盖由相交沟槽限定的电池角部的穿通抑制块，其中设置在紧邻沟槽的角下方的源极区域具有比剩余部分更低的第一导电类型的杂质的净浓度的源地区。

5. 发明授权

US5907169A Self-aligned and process-adjusted high density power transistor with gate sidewalls provided with punch through prevention and reduced JFET resistance 失效
标题翻译：自对准和工艺调节的高密度功率晶体管，栅极侧壁提供穿孔防止和减小的JFET电阻
公开(公告)号：US5907169A
公开(公告)日：1999-05-25
申请号：US844165
申请日：1997-04-18
申请人： Fwu-Iuan Hshieh , True-Lon Lin , Koon Chong So
发明人： Fwu-Iuan Hshieh , True-Lon Lin , Koon Chong So
IPC分类号： H01L21/28 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L21/28114 , H01L21/2815 , H01L29/402 , H01L29/0638 , H01L29/0847 , H01L29/4232 , H01L29/4238
摘要： The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary. The MOSFET transistor further includes a thin gate oxide layer overlying the top surface of the substrate and an edge of the raised oxide terrace. The MOSFET transistor further includes a polysilicon gate overlaying the oxide block and the silicon terrace, the gate further covering an area above the source region and the body region insulated by the gate oxide layer therefrom.
摘要翻译：本发明公开了一种支撑在基板上的MOSFET晶体管。 MOSFET晶体管包括在衬底的顶表面附近限定其中的漏极区的第一导电类型的外延层。 MOSFET晶体管还包括负载在外延层的凸起的硅平台上的氧化物块，该外延层设置在晶体管的中心部分的第一导电类型比外延层高的掺杂剂浓度的JFET还原区之上。 MOSFET晶体管还包括围绕设置在顶表面附近并限定MOSFET晶体管的边界的JFET还原区的第二导电类型的下外体体区域。 MOSFET晶体管还包括封装在设置在顶表面附近并延伸到晶体管边界的下外体体区中的第一导电类型的源极区域。 MOSFET晶体管还包括覆盖在衬底的顶表面上的薄栅极氧化物层和凸起的氧化物露台的边缘。所述MOSFET晶体管还包括覆盖所述氧化物块和所述硅平台的多晶硅栅极，所述栅极还覆盖所述源极区域上方的区域以及由所述栅极氧化物层绝缘的所述主体区域。

6. 发明授权

US5729037A MOSFET structure and fabrication process for decreasing threshold voltage 失效
标题翻译： MOSFET结构和降低阈值电压的制造工艺
公开(公告)号：US5729037A
公开(公告)日：1998-03-17
申请号：US638639
申请日：1996-04-26
申请人： Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Danny Chi Nim , Koon Chong So
发明人： Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Danny Chi Nim , Koon Chong So
IPC分类号： H01L21/336 , H01L29/36 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66712 , H01L29/086 , H01L29/1095 , H01L29/7811 , H01L29/36
摘要： Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve a low threshold voltage. The improved MOSFET device is formed in a semiconductor substrate with a drain region formed near a bottom surface of the substrate supporting a plurality of double-diffused vertical cells thereon wherein each of the vertical cells including a pn-junction having a body region surrounding a source region and each of the vertical cell further including a gate above the pn-junction. Each of the vertical cells further includes a source-dopant segregation reduction layer for reducing a surface segregation between the source region and an oxide layer underneath the gate whereby the body surface peak dopant concentration near an interface between the source region and the body region is reduced for reducing a threshold voltage of the MOSFET device. In another preferred embodiment, the source-dopant segregation reduction layer includes a LPCVD nitride layer formed on top of the polysilicon gates.
摘要翻译：在本发明中公开了改进的功率MOSFET结构和制造工艺以实现低阈值电压。改进的MOSFET器件形成在半导体衬底中，其中在衬底的底表面附近形成有漏极区域，该漏极区域支撑多个双扩散垂直电池，其中每个垂直单元包括具有围绕源极的体区的pn结区域，并且每个垂直单元还包括在pn结上方的栅极。每个垂直单元还包括用于减少源极区域和栅极之下的氧化物层之间的表面偏析的源极 - 掺杂剂偏析还原层，从而源极区域和体区域之间的界面附近的体表面峰值掺杂剂浓度降低用于降低MOSFET器件的阈值电压。在另一个优选的实施方案中，源 - 掺杂剂分离还原层包括形成在多晶硅栅极顶部的LPCVD氮化物层。

7. 发明授权

US5923065A Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings 失效
标题翻译：功率MOSFET器件采用简化的制造工艺制造，以实现更好的耐用性和产品成本节省
公开(公告)号：US5923065A
公开(公告)日：1999-07-13
申请号：US661952
申请日：1996-06-12
申请人： Koon Chong So , Danny Chi Nim , True-Lon Lin , Fwu-Iuan Hshieh , Yan Man Tsui
发明人： Koon Chong So , Danny Chi Nim , True-Lon Lin , Fwu-Iuan Hshieh , Yan Man Tsui
IPC分类号： H01L21/336 , H01L29/10 , H01L29/76
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/7811 , H01L29/0619 , H01L29/0638 , H01L29/402
摘要： This invention discloses a MOSFET device in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region, doped with impurities of a first conductivity type, formed in the semiconductor chip near the bottom surface. The MOSFET device further includes a vertical pn-junction region, which includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region wherein the lower-outer body region defining a channel region extending from the source region to the drain region near the top surface. The MOSFET device further includes a gate formed on top of the channel region on the top surface. The gate includes a thin insulative bottom layer for insulating from the channel region. The gate is provided for applying a voltage thereon for controlling a current flowing from the source region to the drain region via the channel region. The MOSFET device further includes a deep heavily doped body-dopant region disposed immediately below the source region in the lower-outer body region. It is implanted with a higher concentration of dopant than the lower-outer body region whereby a device ruggedness of the MOSFET device is improved. The deep heavily-doped body-dopant region having a body-dopant concentration profile defined by a diffusion of the body-dopant from an implant depth about twice as that of a source implant-depth whereby the deep heavily-doped body dopant region is kept at a distance away from the channel region.
摘要翻译：本发明公开了一种具有顶表面和底表面的半导体芯片中的MOSFET器件。 MOSFET器件包括在底表面附近形成在半导体芯片中的掺杂有第一导电类型的杂质的漏极区域。 MOSFET器件还包括垂直pn结区域，其包括形成在漏极区域的顶部上的掺杂有第二导电类型的杂质的下外部体区域。 pn结区域还包括掺杂有第一导电类型的杂质的源区，形成在下外体区域的顶部，其中下外体体区限定从源区延伸到漏区的沟道区靠近顶面。 MOSFET器件还包括形成在顶表面上的沟道区域的顶部上的栅极。栅极包括用于与沟道区绝缘的薄绝缘底层。栅极用于在其上施加电压以控制经由沟道区域从源极区域流到漏极区域的电流。 MOSFET器件还包括深下部重掺杂体 - 掺杂区域，其设置在下外体区域中的源极区域的正下方。注入比下外体区域更高浓度的掺杂剂，从而提高MOSFET器件的器件耐用性。深掺杂的体 - 掺杂剂区域具有由植入深度约为原始植入深度的两倍的体掺杂物的扩散所限定的体 - 掺杂物浓度分布，从而保留深重掺杂体掺杂区域距离通道区域一定距离。

8. 发明授权

US5668026A DMOS fabrication process implemented with reduced number of masks 失效
标题翻译： DMOS制造工艺以减少数量的掩模实现
公开(公告)号：US5668026A
公开(公告)日：1997-09-16
申请号：US611745
申请日：1996-03-06
申请人： True-Lon Lin , Fwu-Iuan Hshieh , Danny Chi Nim , Koon Chong So , Yan Man Tsui
发明人： True-Lon Lin , Fwu-Iuan Hshieh , Danny Chi Nim , Koon Chong So , Yan Man Tsui
IPC分类号： H01L21/265 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/1095 , H01L29/66712 , H01L29/7813 , H01L29/0847 , H01L29/41766
摘要： A new DMOS fabrication process is disclosed. The fabrication process includes the steps of (a) growing an oxide layer on the substrate; (b) applying a first mask to define an active area and for selectively patterning the oxide layer for keeping a plurality of source implant blocking stumps near a plurality source regions wherein the blocking stumps being formed with width greater than twice a diffusion length of a source dopant and with width less than twice a diffusion length of the body dopant whereby the body regions merging together in the body diffusion becoming a single body region underneath the blocking stumps; (c) applying a second mask for forming a plurality of gates covering a portion of areas between the blocking stumps defining an implant window; (d) implanting a body dopant through the implant window followed by a body diffusion for forming a body region underneath the blocking stumps; (e) implanting the source dopant through the implant window over the source implant blocking stumps following by a source diffusion for forming separate source regions underneath the blocking stumps; (f) depositing an insulating dielectric BPSG/PSG layer; (g) employing a contact mask for etching through the insulating dielectric BPSG/PSG layer and the source implant blocking stumps to define contact windows; (h) depositing a metal layer to form a contact layer through the contact window; and (i) patterning the metal layer with a metal contact to define a plurality of contacts whereby the transistor is fabricated with a four masks process.
摘要翻译：公开了一种新的DMOS制造工艺。制造工艺包括以下步骤：（a）在衬底上生长氧化物层; （b）施加第一掩模以限定有源区域并且用于选择性地图案化氧化物层，以便在多个源区域附近保持多个源注入阻挡块，其中形成的阻挡树脂的宽度大于源的扩散长度的两倍掺杂剂并且具有小于体掺杂物的扩散长度的两倍的宽度，从而身体区域在体扩散中合并在一起成为阻塞树桩下方的单个体区域; （c）施加第二掩模以形成覆盖限定植入窗口的阻挡树脂之间的区域的一部分的多个栅极; （d）通过植入窗口植入体内掺杂剂，随后进行体扩散，以形成阻挡树脂下面的体区; （e）在源极注入之后，通过源极扩散将源极掺杂剂注入到植入物窗口上，随后通过源极扩散在阻挡树脂下方形成分离的源区; （f）沉积绝缘介电BPSG / PSG层; （g）使用接触掩模通过绝缘电介质BPSG / PSG层和源极注入阻挡块蚀刻以限定接触窗口; （h）沉积金属层以通过所述接触窗形成接触层; 和（i）用金属接触图案化金属层以限定多个触点，由此通过四个掩模工艺制造晶体管。

9. 发明授权

US07364994B2 Method for manufacturing a superjunction device with wide mesas 失效
标题翻译：制造具有宽台面的超级结装置的方法
公开(公告)号：US07364994B2
公开(公告)日：2008-04-29
申请号：US11420490
申请日：2006-05-26
申请人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , Brian D. Pratt
IPC分类号： H01L21/425 , H01L21/336 , H01L21/332 , H01L21/44 , H01L23/58
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
摘要翻译：制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。至少一个台面具有第一和第二侧壁。该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。最后，沟槽填充绝缘材料。

10. 发明授权

US07015125B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
公开(公告)号：US07015125B2
公开(公告)日：2006-03-21
申请号：US10983490
申请日：2004-11-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式