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1. 发明授权

US07015125B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
公开(公告)号：US07015125B2
公开(公告)日：2006-03-21
申请号：US10983490
申请日：2004-11-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

2. 发明授权

US06657254B2 Trench MOSFET device with improved on-resistance 有权
公开(公告)号：US06657254B2
公开(公告)日：2003-12-02
申请号：US09999116
申请日：2001-11-21
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0878
摘要： A trench MOSFET device and method of making the same. The trench MOSFET device comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial region from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a doped region of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (g) a body region of a second conductivity type formed within an upper portion of the epitaxial layer and adjacent the trench, wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench; and (h) a source region of the first conductivity type formed within an upper portion of the body region and adjacent the trench. The presence of the doped region lying between the bottom portion of the trench and the substrate (also referred to herein as a “trench bottom implant”) serves to reduce the on-resistance of the device.

3. 发明授权

US06822288B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
标题翻译：沟槽MOSFET器件，具有多晶硅源接触结构
公开(公告)号：US06822288B2
公开(公告)日：2004-11-23
申请号：US10010484
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.
摘要翻译：沟槽MOSFET晶体管器件及其制造方法。该装置包括：（a）第一导电类型的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）第二导电类型的体区，设置在所述外延层的上部并且与所述沟槽相邻; （g）第一导电类型的源极区域，设置在所述主体区域的上部并且邻近所述沟槽; （h）第二导电类型的上部区域，在所述主体区域的上部并且邻近所述源极区域，所述上部区域具有比所述身体区域更高的载流子浓度; 和（i）设置在所述外延层上表面上的源极接触区域，其中所述源极接触区域包括与所述源极区域电接触的掺杂多晶硅接触区域以及与所述源极区域电接触的相邻金属接触区域和上部区域。

4. 发明授权

US07094640B2 Method of making a trench MOSFET device with improved on-resistance 有权
标题翻译：制造具有改善的导通电阻的沟槽MOSFET器件的方法
公开(公告)号：US07094640B2
公开(公告)日：2006-08-22
申请号：US10725325
申请日：2003-12-01
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878
摘要： A method of forming a trench MOSFET device includes depositing an epitaxial layer over a substrate, both having the first conductivity type, the epitaxial layer having a lower majority carrier concentration than the substrate, forming a body region of a second conductivity type within an upper portion of the epitaxial layer, etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer, the trench extending to a greater depth from the upper surface of the epitaxial layer than the body region, forming a doped region of the first conductivity type between a bottom portion of the trench and substrate, the doped region having a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer, wherein the doped region is diffused and spans 100% of the distance from the trench bottom portion to the substrate, forming an insulating layer lining at least a portion of the trench, forming a conductive region within the trench adjacent the insulating layer and forming a source region of said first conductivity type within an upper portion of the body region and adjacent the trench.
摘要翻译：形成沟槽MOSFET器件的方法包括在衬底上沉积外延层，二者具有第一导电类型，外延层具有比衬底更低的多数载流子浓度，在上部形成第二导电类型的体区从外延层的上表面蚀刻延伸到外延层中的沟槽，沟槽从外延层的上表面延伸到比体区更大的深度，形成第一导电性的掺杂区域类型在沟槽的底部和衬底之间，掺杂区域具有比衬底的载流子浓度低的多数载流子浓度，并且高于外延层的掺杂区域，其中掺杂区域扩散并且跨越距离的距离的100％沟槽底部到衬底，形成衬里至少一部分沟槽的绝缘层，形成导电区域wi 使邻近绝缘层的沟槽变薄，并在所述体区域的上部并且邻近所述沟槽形成所述第一导电类型的源极区域。

5. 发明授权

US06548860B1 DMOS transistor structure having improved performance 有权
标题翻译： DMOS晶体管结构具有改进的性能
公开(公告)号：US06548860B1
公开(公告)日：2003-04-15
申请号：US09515335
申请日：2000-02-29
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/0865 , H01L29/1095 , H01L29/7811
摘要： A trench DMOS transistor structure is provided that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region of the first conductivity type in the body region adjacent to the trench.
摘要翻译：提供沟槽DMOS晶体管结构，其包括形成在第一导电类型的衬底上的至少三个单独沟槽DMOS晶体管单元。多个独立的DMOS晶体管单元可分为外围晶体管单元和内部晶体管单元。每个单独的晶体管单元包括位于基板上的体区，其具有第二导电类型。至少一个沟槽延伸穿过身体区域和衬底。绝缘层对沟槽进行排列。导电电极位于沟槽中，覆盖绝缘层。内部晶体管单元，但不是外围晶体管单元，每个还包括与沟槽相邻的体区中的第一导电类型的源极区域。

6. 发明授权

US5877529A Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness 失效
标题翻译： Mosfet终端设计和核心单元配置，以增加击穿电压并提高器件的耐用性
公开(公告)号：US5877529A
公开(公告)日：1999-03-02
申请号：US978667
申请日：1997-11-26
申请人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
发明人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/76 , H01L23/58 , H01L29/94
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/7811 , H01L29/0696 , H01L2924/0002
摘要： Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve higher breakdown voltage and improved device ruggedness. The power transistor includes a core cell area which includes a plurality of power transistor cells and a termination area. The power transistor further includes an outer pickup guarding ring, disposed in the termination area guarding the core cell area, for picking up free charged-particles generated in the termination area for preventing the free charged particles from entering the core cell area. In another preferred embodiment, the power transistor further includes an inner pickup guarding fence and blocks, disposed between the termination area and the core cell area for picking up free charged-particles not yet picked up by the outer pickup guarding ring for preventing the free charged particles from entering the core cell area.
摘要翻译：在本发明中公开了改进的功率MOSFET结构和制造工艺，以实现更高的击穿电压和改进的器件耐用性。功率晶体管包括包含多个功率晶体管单元和端接区域的核心单元区域。功率晶体管还包括外部拾波器保护环，设置在保护核心单元区域的端接区域中，用于拾取终止区域中产生的免费带电粒子，以防止自由带电粒子进入核心单元区域。在另一个优选实施例中，功率晶体管还包括内部拾取器防护栅栏和块，其设置在终端区域和核心单元区域之间，用于拾取由外部拾音器保护环尚未拾取的免费带电粒子，以防止自由充电颗粒进入核心区域。

7. 发明授权

US06762098B2 Trench DMOS transistor with embedded trench schottky rectifier 有权
标题翻译：沟槽DMOS晶体管采用嵌入式沟道肖特基整流器
公开(公告)号：US06762098B2
公开(公告)日：2004-07-13
申请号：US10448791
申请日：2003-05-30
申请人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
发明人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/7806 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.
摘要翻译：一种在一个或多个整流器区域内具有多个沟道肖特基势垒整流器的集成电路以及一个或多个晶体管区域内的多个沟槽DMOS晶体管。集成电路包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的掺杂水平; （c）晶体管区域中的外延层内的第二导电类型的多个体区; （d）在所述晶体管区域和所述整流器区域中的所述外延层内的多个沟槽;（e）对所述沟槽进行排列的第一绝缘层; （f）沟槽内的多晶硅导体并覆盖第一绝缘层; （g）在与所述沟槽相邻的位置处的所述主体区域内的所述第一导电类型的多个源极区域; （h）晶体管区域上的掺杂多晶硅层上的第二绝缘层; 和（i）在晶体管区域和整流器区域上的电极层。

8. 发明授权

US06518152B2 Method of forming a trench schottky rectifier 失效
标题翻译：形成沟槽肖特基整流器的方法
公开(公告)号：US06518152B2
公开(公告)日：2003-02-11
申请号：US10043633
申请日：2002-01-10
申请人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2128
CPC分类号： H01L29/8725 , H01L29/872
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
摘要翻译：提供肖特基整流器。肖特基整流器包括：（a）具有第一和第二相对面的半导体区域，半导体区域包括邻近第一面的第一导电类型的阴极区域和与第二面相邻的第一导电类型的漂移区域，以及漂移区具有比阴极区更低的净掺杂浓度; （b）从所述第二面延伸到所述半导体区域并限定所述半导体区域内的一个或多个台面的一个或多个沟槽; （c）与沟槽下部的半导体区相邻的绝缘区; （d）和阳极电极（i）在第二面处与半导体相邻并形成肖特基整流接触，（ii）与沟槽上部的半导体区域相邻并形成肖特基整流接触，以及（iii）与沟槽下部的绝缘区域相邻。

9. 发明授权

US5895951A MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches 失效
标题翻译：通过掺杂沟槽形成深而窄的掺杂区域来实现MOSFET结构和制造工艺
公开(公告)号：US5895951A
公开(公告)日：1999-04-20
申请号：US628493
申请日：1996-04-05
申请人： Koon Chong So , Yan Man Tsui , Fwu-Iuan Hshieh , True-Lon Lin , Danny Chi Nim
发明人： Koon Chong So , Yan Man Tsui , Fwu-Iuan Hshieh , True-Lon Lin , Danny Chi Nim
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/0696 , H01L29/0847
摘要： This invention discloses a MOSFET device which includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough. Each of the vertical cells is surrounded by a polysilicon layer acting as a gate for controlling the source-to-drain current through the channel. The MOSFET device further include a plurality of doping trenches filled with trench-filling materials, The MOSFET device further includes a plurality of deep-doped regions disposed underneath the doping trenches wherein the deep-doped region extends downwardly to a depth which is substantially a sum of an implant depth of the deep-doped region and a vertical diffusion depth below a bottom of the doping trenches.
摘要翻译：本发明公开了一种MOSFET器件，其包括多个垂直单元，每个垂直单元包括源极，漏极和用于通过其传导源极 - 漏极电流的沟道。每个垂直单元被用作控制通过通道的源极 - 漏极电流的栅极的多晶硅层包围。 MOSFET器件还包括填充有沟槽填充材料的多个掺杂沟槽。MOSFET器件还包括设置在掺杂沟槽下方的多个深掺杂区域，其中深掺杂区域向下延伸到基本上为总和的深度的深掺杂区域的注入深度和在掺杂沟槽的底部下方的垂直扩散深度。

10. 发明授权

US5883416A Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage 失效
标题翻译：栅极接触结构，防止接触金属穿过栅极层而不影响击穿电压
公开(公告)号：US5883416A
公开(公告)日：1999-03-16
申请号：US792226
申请日：1997-01-31
申请人： True-Lon Lin , Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
发明人： True-Lon Lin , Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L23/485 , H01L23/48
CPC分类号： H01L29/42368 , H01L29/7811 , H01L29/0696 , H01L29/42372 , H01L29/4238 , H01L2924/0002
摘要： The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.
摘要翻译：本发明公开了一种设置在基板上的功率晶体管。功率器件包括核心单元区域，其包括多个功率晶体管单元，每个功率晶体管单元具有漏极和源极。每个功率晶体管单元还具有形成在衬底上的多晶硅栅极，作为覆盖衬底的多晶硅栅极层的一部分。多晶硅栅极层包括延伸到栅极接触区域的多个多晶栅极层延伸部分，用于与设置在其上的接触金属形成栅极接触。功率晶体管还包括多个耐接触金属焊盘，每个包括设置在多晶栅极层延伸下方的栅极接触区下方的厚氧化物焊盘，由此接触金属电阻焊盘抵抗接触金属穿透其中并且短于底物置于其下。

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