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    • 2. 发明授权
    • TFT SAS memory cell structures
    • TFT SAS存储单元结构
    • US08513079B2
    • 2013-08-20
    • US12259144
    • 2008-10-27
    • Fumitake Mieno
    • Fumitake Mieno
    • H01L21/336
    • H01L21/28282H01L29/4234H01L29/517H01L29/66757H01L29/66833H01L29/792
    • A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an aluminum oxide layer overlying the P− polysilicon layer; and at least one control gate overlying the aluminum oxide layer. In a specific embodiment, the control gate is made of highly doped P+ polysilicon. A method for making the TFT SAS memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
    • 提供一种具有薄膜晶体管(TFT)硅 - 氧化铝 - 硅(SAS)存储单元结构的器件。 该器件包括衬底,衬底上的电介质层,以及嵌入电介质层中的一个或多个源极或漏极区域。 介电层与第一表面相关联。 所述一个或多个源区或漏区中的每一个包括在导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。 另外,该器件包括覆盖共面表面的P-多晶硅层,覆盖在P-多晶硅层上的氧化铝层; 以及覆盖氧化铝层的至少一个控制栅极。 在具体实施例中,控制栅由高掺杂P +多晶硅制成。 提供了用于制造TFT SAS存储单元结构的方法,并且可以重复三维地集成结构。
    • 4. 发明授权
    • Semiconductor device with amorphous silicon mas memory cell structure and manufacturing method thereof
    • 具有非晶硅mas存储单元结构的半导体器件及其制造方法
    • US08105920B2
    • 2012-01-31
    • US12259015
    • 2008-10-27
    • Fumitake Mieno
    • Fumitake Mieno
    • H01L21/00
    • H01L29/792H01L27/11568H01L27/12H01L29/8616
    • A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.
    • 具有非晶硅(a-Si)金属 - 氧化铝半导体(MAS)存储单元结构的半导体器件。 该器件包括衬底,覆盖在衬底上的电介质层,以及嵌入电介质层中的一个或多个源极或漏极区域,其中n型a-Si的共面表面和电介质层。 另外,器件包括p-i-n a-Si二极管结。 该器件还包括在a-Si p-i-n二极管结上的氧化铝电荷俘获层和覆盖氧化铝层的金属控制栅极。 提供了一种用于制造a-Si MAS存储单元结构并且可以重复三维地集成结构的方法。
    • 5. 发明申请
    • METHOD OF RAPID THERMAL TREATMENT USING HIGH ENERGY ELECTROMAGNETIC RADIATION OF A SEMICONDUCTOR SUBSTRATE FOR FORMATION OF EPITAXIAL MATERIALS
    • 使用半导体基板的高能电磁辐射形成外源材料的快速热处理方法
    • US20110065281A1
    • 2011-03-17
    • US12869620
    • 2010-08-26
    • DAVID GAOFumitake Mieno
    • DAVID GAOFumitake Mieno
    • H01L21/306
    • H01L21/02057H01L21/823807H01L21/823814H01L29/7848
    • A method for fabricating semiconductor devices includes providing a semiconductor substrate having a surface region containing one or more contaminants and having an overlying oxide layer. In an embodiment, the one or more contaminants are at least a carbon species. The method includes processing the surface region using at least a wet processing process to selectively remove the overlying oxide layer and expose the surface region including the one or more contaminants. The method includes subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants. The method includes removing the high energy electromagnetic radiation to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.
    • 一种制造半导体器件的方法包括提供具有包含一种或多种污染物并具有上覆氧化物层的表面区域的半导体衬底。 在一个实施方案中,一种或多种污染物是至少一种碳物质。 该方法包括使用至少湿法处理工艺来处理表面区域,以选择性地去除上覆的氧化物层并暴露包括一种或多种污染物的表面区域。 该方法包括使表面区域经受约300至约800纳米的波长范围为小于1秒的高能电磁辐射,以将表面区域的温度升高到大于1000摄氏度,以除去一个 或更多的污染物。 该方法包括去除高能量电磁辐射,以在小于1秒的时间段内将温度降低到约300至约600摄氏度。
    • 6. 发明授权
    • Atomic layer deposition method and semiconductor device formed by the same
    • 原子层沉积法和由其形成的半导体器件
    • US07709386B2
    • 2010-05-04
    • US12141045
    • 2008-06-17
    • Hua JiMin-Hwa ChiFumitake Mieno
    • Hua JiMin-Hwa ChiFumitake Mieno
    • H01L21/44
    • H01L21/0228C23C16/45529H01L21/0214H01L21/0217H01L21/02211H01L21/28282H01L21/3141H01L21/31645H01L21/318H01L21/3185H01L27/11563
    • There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.
    • 提供了一种制造半导体器件的方法,包括以下步骤:将第一前体气体流到ALD室内的半导体衬底,以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应,从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。 还提供了一种半导体器件,其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的介电层。
    • 7. 发明申请
    • Method for Rapid Thermal Treatment Using High Energy Electromagnetic Radiation of a Semiconductor Substrate for Formation of Dielectric Films
    • 用于形成介质膜的半导体基板的高能电磁辐射的快速热处理方法
    • US20100009528A1
    • 2010-01-14
    • US12259095
    • 2008-10-27
    • David GAOFumitake Mieno
    • David GAOFumitake Mieno
    • H01L21/28H01L21/31
    • H01L21/31654H01L21/02233H01L21/268H01L21/2686H01L21/28211H01L21/28282
    • A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections. In a specific embodiment, the oxide layer is a gate oxide layer.
    • 一种制造半导体器件的方法,例如SONOS电池。 该方法包括提供具有自然氧化物层的具有表面区域的半导体衬底(例如,硅晶片,绝缘体上硅)。 该方法包括将表面区域处理为湿清洗工艺以从表面区域去除自然氧化物层。 在一个具体实施方案中,该方法包括使表面区域承受含氧环境,并使表面区域经受波长为约300至约800纳米的高能电磁辐射,持续时间小于10毫秒至 将表面区域的温度增加到大于1000摄氏度。 在一个具体实施方案中,该方法导致形成厚度小于10埃的氧化物层。 在优选实施例中,氧化物层基本上没有针孔和其它缺陷。 在具体实施方案中,氧化物层是栅极氧化物层。
    • 10. 发明授权
    • Semiconductor device and related manufacturing method
    • 半导体器件及相关制造方法
    • US08872243B2
    • 2014-10-28
    • US13618004
    • 2012-09-14
    • Fumitake Mieno
    • Fumitake Mieno
    • H01L29/76H01L27/12H01L21/84H01L21/8238H01L21/302
    • H01L29/66795H01L29/785
    • A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.
    • 半导体器件制造方法包括在半导体部件上设置掩模。 该方法还包括提供虚拟元件以覆盖与半导体部件的第一部分重叠并覆盖半导体部件的第二部分的掩模的一部分。 该方法还包括去除未被掩模或虚拟元件覆盖的半导体部件的第三部分。 该方法还包括提供接触半导体部件的第一部分的硅化合物。 该方法还包括去除虚设元件以暴露并移除半导体部件的第二部分。 该方法还包括形成与半导体部件的第一部分重叠的栅极结构。 半导体部件的第一部分用作沟道区域并由硅化合物支撑。