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1. 发明申请

US20110293046A1 COMPLEX SIGNAL PROCESSING CIRCUIT, RECEIVER CIRCUIT, AND SIGNAL REPRODUCTION DEVICE 有权
标题翻译：复合信号处理电路，接收器电路和信号再现装置
公开(公告)号：US20110293046A1
公开(公告)日：2011-12-01
申请号：US13206226
申请日：2011-08-09
申请人： Fumiaki Senoue , Kouichi Nagano
发明人： Fumiaki Senoue , Kouichi Nagano
IPC分类号： H04L27/06 , H03M1/12
CPC分类号： H04B1/30 , H03D3/009 , H04L27/3863
摘要： An analog complex filter combines an in-phase signal and a quadrature signal to output first and second analog signals. An analog-to-digital converter converts the first and second analog signals into first and second digital signals. A digital complex filter attenuates components corresponding to the quadrature signal and the in-phase signal of the first and second digital signals, respectively. A digital bandwidth limited filter allows a target component and an image component contained in the digital complex signal composed of the first and second digital signals from the digital complex filter to pass therethrough, and attenuates an adjacent interference component. An IQ imbalance correction circuit corrects a quadrature error and an amplitude error between the first and second digital signals from the digital band-pass filter.
摘要翻译：模拟复合滤波器将同相信号和正交信号组合以输出第一和第二模拟信号。模数转换器将第一和第二模拟信号转换成第一和第二数字信号。数字复合滤波器分别衰减对应于第一和第二数字信号的正交信号和同相信号的分量。数字带宽限制滤波器允许包含在由数字复合滤波器的第一和第二数字信号组成的数字复合信号中的目标分量和图像分量通过，并衰减相邻的干扰分量。 IQ失衡校正电路校正的正交误差，并从所述数字带通滤波器的第一和第二数字信号之间的振幅误差。

2. 发明授权

US08223902B2 Complex signal processing circuit, receiver circuit, and signal reproduction device 有权
标题翻译：复信号处理电路，接收电路和信号再现装置
公开(公告)号：US08223902B2
公开(公告)日：2012-07-17
申请号：US13206226
申请日：2011-08-09
申请人： Fumiaki Senoue , Kouichi Nagano
发明人： Fumiaki Senoue , Kouichi Nagano
IPC分类号： H03D1/04 , H04B1/10
CPC分类号： H04B1/30 , H03D3/009 , H04L27/3863
摘要： An analog complex filter combines an in-phase signal and a quadrature signal to output first and second analog signals. An analog-to-digital converter converts the first and second analog signals into first and second digital signals. A digital complex filter attenuates components corresponding to the quadrature signal and the in-phase signal of the first and second digital signals, respectively. A digital bandwidth limited filter allows a target component and an image component contained in the digital complex signal composed of the first and second digital signals from the digital complex filter to pass therethrough, and attenuates an adjacent interference component. An IQ imbalance correction circuit corrects a quadrature error and an amplitude error between the first and second digital signals from the digital band-pass filter.
摘要翻译：模拟复合滤波器将同相信号和正交信号组合以输出第一和第二模拟信号。模数转换器将第一和第二模拟信号转换成第一和第二数字信号。数字复合滤波器分别衰减对应于第一和第二数字信号的正交信号和同相信号的分量。数字带宽限制滤波器允许包含在由数字复合滤波器的第一和第二数字信号组成的数字复合信号中的目标分量和图像分量通过，并衰减相邻的干扰分量。 IQ不平衡校正电路校正来自数字带通滤波器的第一和第二数字信号之间的正交误差和振幅误差。

3. 发明授权

US08648632B2 Digital PLL circuit, semiconductor integrated circuit, and display apparatus 有权
标题翻译：数字PLL电路，半导体集成电路和显示装置
公开(公告)号：US08648632B2
公开(公告)日：2014-02-11
申请号：US13313638
申请日：2011-12-07
申请人： Hiroki Mouri , Kouji Okamoto , Fumiaki Senoue
发明人： Hiroki Mouri , Kouji Okamoto , Fumiaki Senoue
IPC分类号： H03L7/06
CPC分类号： H03D13/003 , H03L7/087 , H03L2207/50
摘要： In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.
摘要翻译：在数字PLL电路中，相位比较电路对参考时钟和振荡时钟的转换次数进行计数，将所参考时钟的转换次数达到参考计数值所花费的时间设置为相位比较时间段，以及将作为相位误差值的目标计数值相对于基准时钟的频率和基准计数值的期望的振荡频率的倍率值与振荡的转移次数进行比较，时钟在相位比较时间段。平滑电路平滑相位误差值。数字控制振荡电路根据平滑电路平滑的相位误差值来控制振荡时钟的频率。

4. 发明授权

US08780974B2 Digital PLL circuit and communication device 有权
标题翻译：数字PLL电路和通信设备
公开(公告)号：US08780974B2
公开(公告)日：2014-07-15
申请号：US13049645
申请日：2011-03-16
申请人： Fumiaki Senoue , Kouji Okamoto
发明人： Fumiaki Senoue , Kouji Okamoto
IPC分类号： H04N7/12 , H03L7/091 , H03L7/087
CPC分类号： H03L7/087 , H03L7/091 , H03L2207/50
摘要： In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.
摘要翻译：在通过将参考信号的频率乘以频率指令字（频率比）而获得的频率输出时钟信号的数字PLL电路中，RPA串行地添加包含分数分量的频率指令字。 RPA的输出被输入到微小的相位误差发生器。相位误差发生器基于频率指令字的串行相加值的小数部分产生接近参考信号的实际振幅值的多个阈值，计算参考信号的振幅值和相位误差的相位误差基于阈值对应于振幅值的参考信号，并计算参考信号和输出时钟之间的微小相位误差。

5. 发明授权

US07769980B2 Parallel operation device allowing efficient parallel operational processing 失效
标题翻译：并行运行装置允许高效的并行运行处理
公开(公告)号：US07769980B2
公开(公告)日：2010-08-03
申请号：US11840116
申请日：2007-08-16
申请人： Toshinori Sueyoshi , Masahiro Iida , Mitsutaka Nakano , Fumiaki Senoue , Katsuya Mizumoto
发明人： Toshinori Sueyoshi , Masahiro Iida , Mitsutaka Nakano , Fumiaki Senoue , Katsuya Mizumoto
IPC分类号： G06F15/80
CPC分类号： G06F9/3879 , G06F9/30036 , G06F9/3887
摘要： In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.
摘要翻译：在对应于条目提供的算术/逻辑单元（ALU）中，提供根据多指令多数据（MIMD）指令产生一组控制信号的MIMD指令解码器和存储指定MIMD指令的数据的MIMD寄存器，提供了一个ALU通信电路。 ALU通信电路的移动量和方向由存储在移动数据寄存器中的数据位来设置。可以对每个ALU单元分别执行移动量和操作指令的数据移动和算术/逻辑运算。因此，在单指令多数据类型处理装置中，可以以灵活的方式高速执行多指令多数据操作。

6. 发明申请

US20080052497A1 PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING 失效
标题翻译：并行操作装置，实现有效的平行运行处理
公开(公告)号：US20080052497A1
公开(公告)日：2008-02-28
申请号：US11840116
申请日：2007-08-16
申请人： Toshinori Sueyoshi , Masahiro Iida , Mitsutaka Nakano , Fumiaki Senoue , Katsuya Mizumoto
发明人： Toshinori Sueyoshi , Masahiro Iida , Mitsutaka Nakano , Fumiaki Senoue , Katsuya Mizumoto
IPC分类号： G06F9/302 , G06F9/305
CPC分类号： G06F9/3879 , G06F9/30036 , G06F9/3887
摘要： In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction Multiple Data (MIME) instruction and an MIMD register storing data designating the MIME instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.
摘要翻译：在对应于条目的算术/逻辑单元（ALU）中，提供根据多指令多数据（MIME）指令产生一组控制信号的MIMD指令解码器和存储指定MIME指令的数据的MIMD寄存器，提供了ALU间通信电路。 ALU通信电路的移动量和方向由存储在移动数据寄存器中的数据位来设置。可以通过为每个ALU单元单独设置的移动量和操作指令执行数据移动和算术/逻辑运算。因此，在单指令多数据类型处理装置中，可以在高执行多指令多数据操作速度灵活。

7. 发明申请

US20120081339A1 DIGITAL PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DISPLAY APPARATUS 有权
标题翻译：数字PLL电路，半导体集成电路和显示设备
公开(公告)号：US20120081339A1
公开(公告)日：2012-04-05
申请号：US13313638
申请日：2011-12-07
申请人： Hiroki MOURI , Kouji Okamoto , Fumiaki Senoue
发明人： Hiroki MOURI , Kouji Okamoto , Fumiaki Senoue
IPC分类号： G09G5/00 , H03L7/08
CPC分类号： H03D13/003 , H03L7/087 , H03L2207/50
摘要： In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.
摘要翻译：在数字PLL电路中，相位比较电路对参考时钟和振荡时钟的转换次数进行计数，将所参考时钟的转换次数达到参考计数值所花费的时间设置为相位比较时间段，以及将作为相位误差值的目标计数值相对于基准时钟的频率和基准计数值的期望的振荡频率的倍率值与振荡的转移次数进行比较，时钟在相位比较时间段。平滑电路平滑相位误差值。数字控制振荡电路根据平滑电路平滑的相位误差值来控制振荡时钟的频率。

8. 发明申请

US20100325386A1 PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING 审中-公开
标题翻译：并行操作装置，实现有效的平行运行处理
公开(公告)号：US20100325386A1
公开(公告)日：2010-12-23
申请号：US12821732
申请日：2010-06-23
申请人： Toshinori Sueyoshi , Masahiro Iida , Mitsutaka Nakano , Fumiaki Senoue , Katsuya Mizumoto
发明人： Toshinori Sueyoshi , Masahiro Iida , Mitsutaka Nakano , Fumiaki Senoue , Katsuya Mizumoto
IPC分类号： G06F15/76
CPC分类号： G06F9/3879 , G06F9/30036 , G06F9/3887
摘要： In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.
摘要翻译：在对应于条目提供的算术/逻辑单元（ALU）中，提供根据多指令多数据（MIMD）指令产生一组控制信号的MIMD指令解码器和存储指定MIMD指令的数据的MIMD寄存器，提供了一个ALU通信电路。 ALU通信电路的移动量和方向由存储在移动数据寄存器中的数据位来设置。可以对每个ALU单元分别执行移动量和操作指令的数据移动和算术/逻辑运算。因此，在单指令多数据类型处理装置中，可以以灵活的方式高速执行多指令多数据操作。

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