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1. 发明申请

US20110303973A1 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD 有权
标题翻译：半导体器件和生产方法
公开(公告)号：US20110303973A1
公开(公告)日：2011-12-15
申请号：US13116506
申请日：2011-05-26
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , King-Jien Chui , Yisuo Li , Yu Jiang , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , King-Jien Chui , Yisuo Li , Yu Jiang , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42392 , H01L21/26586 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L29/42384 , H01L29/4908 , H01L29/4958 , H01L29/66666 , H01L29/66772 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.
摘要翻译：根据本发明的半导体器件是nMOS SGT，并且由第一n +型硅层，含有金属的第一栅电极和第二n +型硅层构成，所述第二n +型硅层布置在垂直定位在第一n +型硅层上的第一柱状硅层的表面上第一平面硅层。此外，第一绝缘膜位于第一栅电极和第一平面硅层之间，第二绝缘膜位于第一栅电极的顶表面上。此外，含有第一栅电极的金属被第一n +型硅层，第二n +型硅层，第一绝缘膜和第二绝缘膜包围。

2. 发明授权

US09153697B2 Surrounding gate transistor (SGT) structure 有权
标题翻译：周边栅晶体管（SGT）结构
公开(公告)号：US09153697B2
公开(公告)日：2015-10-06
申请号：US13116506
申请日：2011-05-26
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , King-Jien Chui , Yisuo Li , Yu Jiang , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , King-Jien Chui , Yisuo Li , Yu Jiang , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
IPC分类号： H01L21/70 , H01L29/786 , H01L21/8238 , H01L29/423 , H01L29/49 , H01L29/66 , H01L21/265
CPC分类号： H01L29/42392 , H01L21/26586 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L29/42384 , H01L29/4908 , H01L29/4958 , H01L29/66666 , H01L29/66772 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.
摘要翻译：根据本发明的半导体器件是nMOS SGT，并且由第一n +型硅层，含有金属的第一栅电极和第二n +型硅层构成，所述第二n +型硅层布置在垂直定位在第一n +型硅层上的第一柱状硅层的表面上第一平面硅层。此外，第一绝缘膜位于第一栅电极和第一平面硅层之间，第二绝缘膜位于第一栅电极的顶表面上。此外，含有第一栅电极的金属被第一n +型硅层，第二n +型硅层，第一绝缘膜和第二绝缘膜包围。

3. 发明授权

US08486785B2 Surround gate CMOS semiconductor device 有权
公开(公告)号：US08486785B2
公开(公告)日：2013-07-16
申请号：US13113482
申请日：2011-05-23
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Yu Jiang , King-Jien Chui , Yisuo Li , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Yu Jiang , King-Jien Chui , Yisuo Li , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
IPC分类号： H01L21/8238
CPC分类号： H01L29/66484 , H01L21/823885 , H01L21/84 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

4. 发明申请

US20110303985A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110303985A1
公开(公告)日：2011-12-15
申请号：US13113482
申请日：2011-05-23
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Yu Jiang , King-Jien Chui , Yisuo Li , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Yu Jiang , King-Jien Chui , Yisuo Li , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66484 , H01L21/823885 , H01L21/84 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.
摘要翻译：半导体器件包括：平面硅层上的柱状硅层; 形成在柱状硅层的底部区域中的第一n +型硅层; 形成在柱状硅层的上部区域的第二n +型硅层; 栅极绝缘膜，形成在第一和第二n +型硅层之间的沟道区的周边; 栅电极，形成在所述栅极绝缘膜的周边，并具有第一金属 - 硅化合物层; 形成在栅电极和平面硅层之间的绝缘膜，形成在柱状硅层的上侧壁中的绝缘膜侧壁; 形成在所述平面硅层中的第二金属 - 硅化合物层; 以及形成在第二n +型硅层上的电接触。

5. 发明授权

US08466512B2 Semiconductor device and production method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08466512B2
公开(公告)日：2013-06-18
申请号：US12858840
申请日：2010-08-18
申请人： Fujio Masuoka , Shintaro Arai , Hiroki Nakamura , Tomohiko Kudo , R. Ramana Murthy , Nansheng Shen , Kavitha Devi Buddharaju , Navab Singh
发明人： Fujio Masuoka , Shintaro Arai , Hiroki Nakamura , Tomohiko Kudo , R. Ramana Murthy , Nansheng Shen , Kavitha Devi Buddharaju , Navab Singh
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/76804 , H01L21/76816 , H01L29/41741 , H01L29/42356 , H01L29/7827
摘要： A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.
摘要翻译：一种制造半导体器件的方法包括制备具有基板，平面半导体层和柱状半导体层的结构，在柱状半导体层的上部形成第二漏极/源极区域，形成接触阻挡膜和触点并在第二漏极/源极区域上形成接触层。形成接触层的步骤包括形成图案，并使用图案将接触层间膜蚀刻到接触阻挡膜，以形成用于接触层的接触孔，并通过蚀刻去除残留在接触孔底部的接触阻挡膜。接触孔的底面向基板的突出部位于形成在柱状半导体层的顶部和侧面上的接触阻挡膜的突出轮廓的圆周上。

6. 发明授权

US08080458B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08080458B2
公开(公告)日：2011-12-20
申请号：US12761735
申请日：2010-04-16
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/42392 , H01L29/458 , H01L29/66666 , H01L29/78642
摘要： A method of manufacturing a semiconductor device includes the steps of forming a first columnar semiconductor layer on a substrate forming a first flat semiconductor layer forming a first semiconductor layer of a second conductive type, and forming a first insulating film. The method further includes the steps of forming a gate insulating film and a gate electrode, forming a second semiconductor layer of the second conductive type, forming a semiconductor layer of a first conductive type and forming a metal-semiconductor compound. The first insulating film has a thickness larger than that of the gate insulating film formed around the first columnar silicon layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在形成第二导电类型的第一半导体层的第一平坦半导体层的基板上形成第一柱状半导体层，形成第一绝缘膜。该方法还包括形成栅绝缘膜和栅电极，形成第二导电类型的第二半导体层的步骤，形成第一导电类型的半导体层并形成金属半导体化合物。第一绝缘膜的厚度大于围绕第一柱状硅层形成的栅极绝缘膜的厚度。

7. 发明授权

US08519475B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08519475B2
公开(公告)日：2013-08-27
申请号：US13289742
申请日：2011-11-04
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
IPC分类号： H01L29/66
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/42392 , H01L29/458 , H01L29/66666 , H01L29/78642
摘要： A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.
摘要翻译：半导体器件包括形成在栅极电极和第一平坦半导体层之间的第一绝缘膜，以及侧壁形状的第二绝缘膜，其形成为围绕第一柱状硅层的上侧壁，同时接触栅电极的上表面和以围绕栅电极和第一绝缘膜的侧壁。半导体器件还包括形成在第一导电类型的第一半导体层的上表面上的第一半导体层的整体或上部形成的金属半导体化合物和第二半导体的上表面形成在第一柱状半导体层的上部的第二导电类型的层。

8. 发明申请

US20100264485A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100264485A1
公开(公告)日：2010-10-21
申请号：US12761735
申请日：2010-04-16
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/42392 , H01L29/458 , H01L29/66666 , H01L29/78642
摘要： This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first insulating film around a lower sidewall of the first columnar silicon layer; forming a gate insulating film and a gate electrode around the first columnar silicon layer; forming a sidewall-shaped second insulating film to surround an upper sidewall of the first columnar silicon layer; forming a semiconductor layer of a first conductive type between the first semiconductor layer of the second conductive type and a second semiconductor layer of the second conductive type; and forming a metal-semiconductor compound on an upper surface of the first semiconductor layer of the second conductive type.
摘要翻译：本发明提供一种制造半导体器件的方法，其包括以下步骤：在第一平坦半导体层上形成第一柱状半导体层; 在所述第一柱状半导体层的下部形成第二导电类型的第一半导体层; 在所述第一柱状硅层的下侧壁周围形成第一绝缘膜; 在第一柱状硅层周围形成栅极绝缘膜和栅电极; 形成侧壁形状的第二绝缘膜以围绕所述第一柱状硅层的上侧壁; 在第二导电类型的第一半导体层和第二导电类型的第二半导体层之间形成第一导电类型的半导体层; 以及在所述第二导电类型的所述第一半导体层的上表面上形成金属 - 半导体化合物。

9. 发明授权

US08395208B2 Semiconductor device and method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08395208B2
公开(公告)日：2013-03-12
申请号：US13478359
申请日：2012-05-23
申请人： Fujio Masuoka , Shintaro Arai , Hiroki Nakamura , Tomohiko Kudo
发明人： Fujio Masuoka , Shintaro Arai , Hiroki Nakamura , Tomohiko Kudo
IPC分类号： H01L29/94 , H01L29/76 , H01L31/062 , H01L31/119 , H01L31/113
CPC分类号： H01L29/78642 , H01L29/42392 , H01L29/66772
摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.
摘要翻译：本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

10. 发明授权

US08241976B2 Semiconductor surrounding gate transistor device and production method therefor 有权
标题翻译：半导体周边栅晶体管器件及其制作方法
公开(公告)号：US08241976B2
公开(公告)日：2012-08-14
申请号：US12704000
申请日：2010-02-11
申请人： Fujio Masuoka , Tomohiko Kudo , Shintaro Arai , Hiroki Nakamura
发明人： Fujio Masuoka , Tomohiko Kudo , Shintaro Arai , Hiroki Nakamura
IPC分类号： H01L21/8232
CPC分类号： H01L29/78642 , H01L22/26
摘要： The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.
摘要翻译：该方法包括以下步骤：在形成在基板上的氧化膜上形成平面半导体层，然后在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在柱状的第一导电型半导体层周围形成栅极电介质膜和由金属制成的栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层。

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