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1. 发明授权

US4684986A Television signal memory-write circuit 失效
标题翻译：电视信号存储器写电路
公开(公告)号：US4684986A
公开(公告)日：1987-08-04
申请号：US730392
申请日：1985-05-03
申请人： Frits A. Steenhof , Petrus W. G. Welles , Petrus A. C. M. Nuijten , Jan van der Meer
发明人： Frits A. Steenhof , Petrus W. G. Welles , Petrus A. C. M. Nuijten , Jan van der Meer
IPC分类号： H04N5/907 , H04N5/91 , H04N5/937 , H04N7/01 , H04N5/04 , H04N5/14
CPC分类号： H04N5/91 , H04N5/907 , H04N5/937
摘要： In a television signal memory write circuit which is synchronized by horizontal and vertical synchronizing signal patterns obtained from the television signal to be entered, the mutual positions of these patterns being measured with the aid of a measuring circuit; and depending on this measurement, the vertical synchronizing signal pattern is delayed by a variable delay circuit such that in practice the patterns are prevented from coinciding, thereby preventing a change in the position of a predetermined line number in the television signal memory circuit. This renders the circuit less sensitive to interference.
摘要翻译：在通过从要输入的电视信号获得的水平和垂直同步信号模式同步的电视信号存储器写入电路中，借助于测量电路来测量这些图案的相互位置; 并且根据该测量，垂直同步信号模式被可变延迟电路延迟，使得在实际中防止图案重合，从而防止电视信号存储电路中预定行号的位置改变。这使得电路对干扰不太敏感。

2. 发明授权

US07728659B2 Arrangement for amplifying a PWM input signal 有权
标题翻译：放大PWM输入信号的布置
公开(公告)号：US07728659B2
公开(公告)日：2010-06-01
申请号：US11815101
申请日：2006-01-20
申请人： Petrus A. C. M. Nuijten , Lutsen L. A. H. Dooper
发明人： Petrus A. C. M. Nuijten , Lutsen L. A. H. Dooper
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.
摘要翻译：脉冲宽度调制（PWM）放大器包括用于重新形成PWM输入信号的脉冲的反馈回路，以通过纠错信号校正放大器的D类输出级中的定时和幅度误差。在这种放大器中，当PWM输入信号的脉冲周期不恒定时，反馈环路给出大量的基带噪声，这尤其是当PWM信号来自噪声整形器时。本发明通过用脉冲周期比例信号修改放大器的整形增益来减少这种噪声。

3. 发明授权

US6157330A Embedding supplemental data in an encoded signal, such as audio / video watermarks 失效
标题翻译：在编码信号中嵌入补充数据，例如音频/视频水印
公开(公告)号：US6157330A
公开(公告)日：2000-12-05
申请号：US13540
申请日：1998-01-26
申请人： Alphons A. M. L. Bruekers , Geert F. G. Depovere , Petrus A. C. M. Nuijten , Arnoldus W. J. Oomen
发明人： Alphons A. M. L. Bruekers , Geert F. G. Depovere , Petrus A. C. M. Nuijten , Arnoldus W. J. Oomen
IPC分类号： H04N19/467 , G06T1/00 , G09C5/00 , G11B20/00 , H03M7/00 , H04N1/387 , H04N7/08 , H04N7/081 , H03M3/00 , H04N7/167
CPC分类号： G06T1/0035 , G11B20/00086 , G11B20/00891 , H04N19/00 , H04N21/23892 , H04N21/8358 , G11B2020/00065
摘要： Method of embedding watermarks in a signal encoded by an encoder having a feedback loop, for example, a sigma-delta modulator (21,22,23). A digital watermark pattern (w) is embedded in the signal (z) by modifying selected samples (for example, replacing every 100th bit) of the encoded signal (y) by samples of the watermark pattern. The circuit (24) for modifying the samples is located inside the loop of the encoder. The effect of watermarking is thus compensated in subsequent encoding steps and the signal-to-noise ratio is only slightly affected.
摘要翻译：在由具有反馈环路的编码器编码的信号中嵌入水印的方法，例如，Σ-Δ调制器（21,22,23）。通过对水印图案的采样修改编码信号（y）的选择样本（例如，每100位替换一次），将数字水印图案（w）嵌入在信号（z）中。用于修改样品的电路（24）位于编码器的环路内。因此，在随后的编码步骤中补偿了水印的效果，并且信噪比仅受到轻微的影响。

4. 发明授权

US5182479A Gate circuit having increased voltage handling capability 失效
标题翻译：门电路具有增加的电压处理能力
公开(公告)号：US5182479A
公开(公告)日：1993-01-26
申请号：US658792
申请日：1991-02-07
申请人： Frank P. Behagel , Tiemen Poorter , Petrus A. C. M. Nuijten
发明人： Frank P. Behagel , Tiemen Poorter , Petrus A. C. M. Nuijten
IPC分类号： H03K17/0812 , H03K17/687
CPC分类号： H03K17/6872 , H03K17/08122
摘要： A gate circuit includes an N-channel and a P-channel insulated gate field-effect transistor whose parallel-connected drain-source paths constitute an analog signal gate and a control circuit, connected to the respective gate electrodes, to turn on and/or turn off the two field-effect transistors. In order to handle signals whose voltage value is higher than the maximum permissible drain-source voltage in the on-state of the N-channel field-effect transistor, means are provided, for turning on the N-channel field-effect transistor at least at a drain-source voltage below a predetermined value. In an embodiment of the invention the means include delay means coupled to the control circuit for turning on the N-channel field-effect transistor with a delay relative to the P-channel field-effect transistor. In another embodiment of the invention the means include switching means arranged in series with the analog signal gate, for temporarily connecting the signal gate to at least one auxiliary voltage.
摘要翻译：栅极电路包括N沟道和P沟道绝缘栅场效应晶体管，其并联连接的漏极 - 源极路径构成模拟信号栅极和连接到各个栅电极的控制电路，以导通和/或关闭两个场效应晶体管。为了处理电压值高于N沟道场效应晶体管的导通状态下的最大允许漏源电压的信号，提供了至少用于接通N沟道场效应晶体管的装置在低于预定值的漏极 - 源极电压下。在本发明的实施例中，装置包括耦合到控制电路的延迟装置，用于以相对于P沟道场效应晶体管的延迟来导通N沟道场效应晶体管。在本发明的另一实施例中，装置包括与模拟信号门串联设置的开关装置，用于将信号门临时连接到至少一个辅助电压。

5. 发明申请

US20080315945A1 Arrangement for Amplifying a Pwm Input Signal 有权
标题翻译：放大Pwm输入信号的布置
公开(公告)号：US20080315945A1
公开(公告)日：2008-12-25
申请号：US11815101
申请日：2006-01-20
申请人： Petrus A. C. M. Nuijten , Lutsen L.A.H. Dooper
发明人： Petrus A. C. M. Nuijten , Lutsen L.A.H. Dooper
IPC分类号： H03F3/00
CPC分类号： H03F3/217
摘要： A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.
摘要翻译：脉冲宽度调制（PWM）放大器包括用于重新形成PWM输入信号的脉冲的反馈回路，以通过纠错信号校正放大器的D类输出级中的定时和幅度误差。在这种放大器中，当PWM输入信号的脉冲周期不恒定时，反馈环路给出大量的基带噪声，这尤其是当PWM信号来自噪声整形器时。本发明通过用脉冲周期比例信号修改放大器的整形增益来减少这种噪声。

6. 发明授权

US06507299B1 Embedding supplemental data in an information signal 失效
标题翻译：在信息信号中嵌入补充数据
公开(公告)号：US06507299B1
公开(公告)日：2003-01-14
申请号：US09426519
申请日：1999-10-26
申请人： Petrus A. C. M. Nuijten
发明人： Petrus A. C. M. Nuijten
IPC分类号： H03M300
CPC分类号： G11B20/00086 , G11B20/00884 , G11B2020/00065 , H04N5/913 , H04N21/23892 , H04N21/8358 , H04N2005/91335
摘要： An arrangement for embedding supplemental data (e.g. a watermark W) in an information signal. In an embodiment of the invention, the arrangement comprises a conventional sigma-delta modulator for encoding an audio signal and modifying means for periodically replacing a bit of the encoded signal by a bit of the watermark. In the same manner, a sync pattern is embedded in the signal. The sync bits are embedded at a smaller distance than the watermark bits. Preferably, the sync pattern is a pattern of contiguous bits which is typically not generated by the encoder. For the sigma-delta modulator, such a pattern is a run of ones followed by a substantially equally long run of zeroes, or vice versa.
摘要翻译：用于将补充数据（例如，水印W）嵌入信息信号中的装置。在本发明的一个实施例中，该装置包括用于对音频信号进行编码的常规Σ-Δ调制器和用于通过一位水印周期性地替换编码信号的位的修改装置。以相同的方式，在信号中嵌入同步模式。同步位以比水印位更小的距离被嵌入。优选地，同步模式是通常不由编码器生成的连续位的模式。对于Σ-Δ调制器，这种模式是一个模式，随后是基本上同样长的零运行，反之亦然。

7. 发明授权

US5243345A Sigma-delta modulator having a plural order loop filter with successive filter sections of successively smaller signal excursion range 失效
标题翻译：具有二次循环过滤器的SIGMA-DELTA调制器，具有成功的小型信号超越范围的连续过滤器部分
公开(公告)号：US5243345A
公开(公告)日：1993-09-07
申请号：US842855
申请日：1992-02-21
申请人： Peter J. A. Naus , Eise C. Dijkmans , Petrus A. C. M. Nuijten
发明人： Peter J. A. Naus , Eise C. Dijkmans , Petrus A. C. M. Nuijten
IPC分类号： H03M3/00 , H03M3/02 , H03M7/34
CPC分类号： H03M7/3035 , H03M3/444 , H03M3/43 , H03M3/452 , H03M7/3028 , H03M7/3037
摘要： A sigma-delta modulator comprising a low-pass filter of the Nth order, which is constituted by a series combination of N first-order integrating sections (6.1, 6.2, 6.3, . . . , 6.N) each comprising an integrator (12.1, 12.2, 12.3, . . . , 12. N) and a limiter (14.1, 14.2, 14.3, . . . , 14.N). The individual output signals of the sections are weighted by means of corresponding weighting amplifiers (16.1, 16.2, 16.3, . . . , 16.N) and the weighted signals are added together by an adder stage (18). The gains of the sections and the limit values of the limiters are selected so that the last limiter (14.N) in the series arrangement is activated first as the input signal level to the sigma-delta modulator increases, then the last-but-one limiter, and so on. This reduces the order of the filter system each time by one section as the input signal level increases above each successive limit value, thereby causing the sigma-delta modulator to remain stable at all signal levels.

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