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1. 发明授权

US06728799B1 Hybrid data I/O for memory applications 有权
标题翻译：用于存储器应用的混合数据I / O
公开(公告)号：US06728799B1
公开(公告)日：2004-04-27
申请号：US09483383
申请日：2000-01-13
申请人： Frederick A. Perner , Kenneth J. Eldredge
发明人： Frederick A. Perner , Kenneth J. Eldredge
IPC分类号： G06F1314
CPC分类号： G11C7/1006 , G11C7/1036 , G11C19/00
摘要： Some forms of memory data I/O requires a parallel interface with the memory array and a serial interface with external data ports to the memory. A hybrid decoder/scan register data I/O scheme is described that offers a high speed data access to selected points along a set of scan registers that connect to the columns (bit lines) of a memory array. The interface to the memory array is a long register which comprises a chain of scan register blocks. Data to and from the memory array is transferred in a parallel manner. Data I/O to a specific memory address or memory data block is routed from a serial data I/O line, through a set of switches controlled by a decoder circuit to the input (or output) port of one of the scan register blocks. This hybrid data I/O circuit offers a high speed access to selected points within the column circuits of a memory array while maintaining an efficient and high speed serial output offered by a scan chain data register.
摘要翻译：存储器数据I / O的一些形式需要与存储器阵列的并行接口以及与存储器的外部数据端口的串行接口。描述了混合解码器/扫描寄存器数据I / O方案，其提供了沿着连接到存储器阵列的列（位线）的一组扫描寄存器的选定点的高速数据访问。与存储器阵列的接口是长寄存器，其包括一连串的扫描寄存器块。往返于存储器阵列的数据以并行方式传送。特定存储器地址或存储器数据块的数据I / O从串行数据I / O线通过由解码器电路控制的一组开关路由到其中一个扫描寄存器块的输入（或输出）端口。该混合数据I / O电路提供对存储器阵列的列电路内的选定点的高速访问，同时保持由扫描链数据寄存器提供的有效和高速的串行输出。

2. 发明授权

US06584589B1 Self-testing of magneto-resistive memory arrays 有权
标题翻译：磁阻存储器阵列的自检
公开(公告)号：US06584589B1
公开(公告)日：2003-06-24
申请号：US09498588
申请日：2000-02-04
申请人： Frederick A. Perner , Kenneth J. Eldredge , Lung Tran
发明人： Frederick A. Perner , Kenneth J. Eldredge , Lung Tran
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C27/02 , G11C29/02 , G11C29/44
摘要： A collection of testing circuits are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays. The combination of testing circuits can detect MRAM array defects including: open rows, shorted memory cells, memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit connecting all the rows to test for open rows and shorted memory cells. A dynamic sense circuit detects whether the resistance of memory cells is within specified limits. An exclusive-OR gate combined with global write controls is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit. Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor or recorded into an on-chip error status table.
摘要翻译：公开了一系列测试电路，可用于形成用于MRAM阵列的综合内置测试系统。测试电路的组合可以检测MRAM阵列缺陷，包括：开放行，短路存储单元，超出电阻规格的存储单元，以及简单的读/写模式错误。内置的测试电路包括连接所有行的线OR电路，以测试打开的行和短路存储单元。动态感测电路检测存储器单元的电阻是否在规定的范围内。与全局写入控制相结合的异或门被集成到读出放大器中，用于执行简单的读写模式测试。来自裕度测试和读写测试的错误数据通过第二个有线电路报告。来自两个有线OR电路和相关行地址的输出被报告给测试处理器或记录在片上错误状态表中。

3. 发明授权

US06873544B2 Triple sample sensing for magnetic random access memory (MRAM) with series diodes 有权
标题翻译：具有串联二极管的磁性随机存取存储器（MRAM）的三次采样检测
公开(公告)号：US06873544B2
公开(公告)日：2005-03-29
申请号：US10696826
申请日：2003-10-30
申请人： Frederick A. Perner , Lung T. Tran , Kenneth J. Eldredge
发明人： Frederick A. Perner , Lung T. Tran , Kenneth J. Eldredge
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15 , G11C11/16 , G11C13/004 , G11C27/02 , G11C2013/0057
摘要： A data storage device that includes an array of resistive memory cells. The resistive memory cells may include a magnetic tunnel junction (MTJ) and a thin-film diode. The device may include a circuit that is electrically connected to the array and that is also capable of monitoring a signal current flowing through a selected memory cell. Once the signal current has been monitored, the circuit is capable of comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the selected memory cell is in. Also, a method for operating the data storage device.
摘要翻译：一种包括电阻式存储单元阵列的数据存储装置。电阻存储单元可以包括磁性隧道结（MTJ）和薄膜二极管。该装置可以包括电连接到阵列的电路，并且还能够监测流过所选择的存储器单元的信号电流。一旦已经监视了信号电流，电路就可以将信号电流与平均参考电流进行比较，以确定所选择的存储单元处于第一电阻状态和第二电阻状态。另外，一种操作方法数据存储设备。

4. 发明授权

US06757188B2 Triple sample sensing for magnetic random access memory (MRAM) with series diodes 有权
公开(公告)号：US06757188B2
公开(公告)日：2004-06-29
申请号：US10151915
申请日：2002-05-22
申请人： Frederick A. Perner , Lung T. Tran , Kenneth J. Eldredge
发明人： Frederick A. Perner , Lung T. Tran , Kenneth J. Eldredge
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C11/16 , G11C13/004 , G11C27/02 , G11C2013/0057
摘要： A data storage device that includes an array of resistive memory cells. The resistive memory cells may include a magnetic tunnel junction (MTJ) and a thin-film diode. The device may include a circuit that is electrically connected to the array and that is also capable of monitoring a signal current flowing through a selected memory cell. Once the signal current has been monitored, the circuit is capable of comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the selected memory cell is in. Also, a method for operating the data storage device.

5. 发明授权

US07376004B2 Increased magnetic memory array sizes and operating margins 有权
标题翻译：增加磁存储器阵列大小和运行裕度
公开(公告)号：US07376004B2
公开(公告)日：2008-05-20
申请号：US10661448
申请日：2003-09-11
申请人： James R. Eaton, Jr. , Frederick A. Perner , Lung T. Tran , Kenneth J. Eldredge
发明人： James R. Eaton, Jr. , Frederick A. Perner , Lung T. Tran , Kenneth J. Eldredge
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C11/16
摘要： A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.
摘要翻译：用于制造磁随机存取存储器（MRAM）的方法在操作期间隔离MRAM阵列中的每个存储单元直到被选择。一些实施例使用用于这种电隔离的串联连接的二极管。只有选定的一个存储器单元将在相应的位和字线之间传导电流。读取和写入数据访问电流的更好，更均匀的分布会导致所有存储单元。在另一个实施例中，该改进用于增加支持较大数据阵列的行数和列数。在另一实施例中，这种改进用于增加操作裕度并减少必要的数据写入电压和电流。

6. 发明授权

US07535754B2 Integrated circuit memory devices with MRAM voltage divider strings therein 有权
标题翻译：具有MRAM分压器串的集成电路存储器件
公开(公告)号：US07535754B2
公开(公告)日：2009-05-19
申请号：US11264539
申请日：2005-11-01
申请人： Frederick A. Perner , Kenneth J. Eldredge
发明人： Frederick A. Perner , Kenneth J. Eldredge
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A memory device and method of reading the memory device is disclosed. The memory device includes a first string of MRAM cells and a second string of MRAM cells. The first string of MRAM cells include a plurality of MRAM cells connected in series and the second string of MRAM cells include another plurality of MRAM cells connected in series. A common connection is controllably connectable to one end of the first string of MRAM cells, and to one end of the second string of MRAM cells.
摘要翻译：公开了一种读取存储器件的存储器件和方法。存储器件包括MRAM单元的第一串和MRAM单元的第二串。 MRAM单元的第一串包括串联连接的多个MRAM单元，并且第二串MRAM单元包括串联连接的另外多个MRAM单元。公共连接可控地连接到MRAM单元的第一串的一端，并连接到第二串MRAM单元的一端。

7. 发明授权

US06262625B1 Operational amplifier with digital offset calibration 有权
标题翻译：具有数字偏移校准的运算放大器
公开(公告)号：US06262625B1
公开(公告)日：2001-07-17
申请号：US09430238
申请日：1999-10-29
申请人： Frederick A. Perner , Kenneth J. Eldredge , Lung T. Tran
发明人： Frederick A. Perner , Kenneth J. Eldredge , Lung T. Tran
IPC分类号： G01R1900
CPC分类号： B82Y10/00 , G11C11/15 , H03F1/304 , H03F3/45771 , H03F2203/45048 , H03F2203/45291 , H03F2203/45342 , H03F2203/45624 , H03F2203/45726
摘要： An operational amplifier includes transistors for providing a controlled current path. At least one of the transistors is in an isolated well in a substrate. Offset of the operational amplifier is corrected by applying a back gate bias voltage to at least one isolated well and changing impedance of the transistors. The proper back gate bias voltage and transistor impedance are determined by incrementally adjusting the back gate bias voltage and then incrementally adjusting the transistor impedance. Calibration values are stored in register memory. Such calibration may be performed by an auto offset calibration process.
摘要翻译：运算放大器包括用于提供受控电流路径的晶体管。至少一个晶体管处于衬底中的隔离阱中。通过对至少一个隔离阱施加背栅偏置电压并改变晶体管的阻抗来校正运算放大器的偏移。正确的背栅偏置电压和晶体管阻抗通过逐步调整背栅偏置电压然后逐渐调整晶体管阻抗来确定。校准值存储在寄存器存储器中。这种校准可以通过自动偏移校准过程来执行。

8. 发明授权

US06188615B1 MRAM device including digital sense amplifiers 有权
标题翻译： MRAM器件包括数字读出放大器
公开(公告)号：US06188615B1
公开(公告)日：2001-02-13
申请号：US09430611
申请日：1999-10-29
申请人： Frederick A. Perner , Kenneth J. Eldredge , Lung T. Tran
发明人： Frederick A. Perner , Kenneth J. Eldredge , Lung T. Tran
IPC分类号： G11C1604
CPC分类号： G11C11/15 , G11C7/067 , G11C16/32
摘要： Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and a digital sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier measures integration time of a signal on the integrator. The signal integration time indicates whether the memory cell MRAM resistance is at a first state (R) or a second state (R+&Dgr;R).
摘要翻译：通过包括直接注入电荷放大器，积分器电容器和数字读出放大器的读取电路来检测磁性随机存取存储器（“MRAM”）器件中的所选存储单元的电阻。直接注入电荷放大器向积分器电容器提供电流，同时在MRAM器件中的未选择的存储单元上保持等电位电压。由于直接注入电荷放大器对所选择的存储单元施加固定电压，所以读出放大器测量积分器上信号的积分时间。信号积分时间表示存储单元MRAM电阻是处于第一状态（R）还是第二状态（R + DELTAR）。

9. 发明授权

US07248306B2 Method of making active matrix display 失效
标题翻译：制作有源矩阵显示的方法
公开(公告)号：US07248306B2
公开(公告)日：2007-07-24
申请号：US10897533
申请日：2004-07-23
申请人： Frederick A. Perner , Krzysztof Nauka
发明人： Frederick A. Perner , Krzysztof Nauka
IPC分类号： G02F1/136
CPC分类号： G02F1/1362 , G02F1/133305 , G02F1/1368 , G02F2001/136295
摘要： A method of making a lower cost active matrix display. In a particular embodiment, the method includes providing at least one first conductor upon a substrate and depositing a gate dielectric upon the first conductor and substrate. At least one paired second conductor and a pixel electrode are deposited upon the gate dielectric, with the second conductor crossing the first conductor and with a narrow gap between the paired second conductor and the pixel electrode. A semiconductor material is deposited over the paired second conductor and pixel electrode, filling the narrow gap. The narrow gap shelters a portion of the semiconductor material, which serves as a semiconductor bridge capable of functioning either as an insulator or as a channel region of a field effect transistor. The remaining, unsheltered semiconductor material is removed. A liquid crystal layer is then deposited upon the paired second conductor, the pixel electrode and the sheltered semiconductor material, and a translucent conductor is deposited upon the liquid crystal display layer. An associated display is also provided.
摘要翻译：制作成本较低的有源矩阵显示的方法。在特定实施例中，该方法包括在衬底上提供至少一个第一导体并在第一导体和衬底上沉积栅极电介质。至少一对成对的第二导体和像素电极沉积在栅极电介质上，其中第二导体与第一导体交叉并且在成对的第二导体和像素电极之间具有窄间隙。半导体材料沉积在成对的第二导体和像素电极上，填充窄间隙。窄间隙避开半导体材料的一部分，其用作能够用作场效应晶体管的绝缘体或沟道区的半导体桥。剩余的未加帽的半导体材料被去除。然后将液晶层沉积在成对的第二导体，像素电极和遮蔽半导体材料上，并且半透明导体沉积在液晶显示层上。还提供了相关联的显示。

10. 发明授权

US07242199B2 Active interconnects and control points in integrated circuits 有权
标题翻译：集成电路中的有源互连和控制点
公开(公告)号：US07242199B2
公开(公告)日：2007-07-10
申请号：US11112795
申请日：2005-04-21
申请人： R. Stanley Williams , Philip J Kuekes , Frederick A. Perner , Greg Snider , Duncan Stewart
发明人： R. Stanley Williams , Philip J Kuekes , Frederick A. Perner , Greg Snider , Duncan Stewart
IPC分类号： G01R27/08
CPC分类号： H05K7/1092 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.
摘要翻译：在本发明的各种实施例中，在集成电路的互连层处引入可调电阻器，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或者在制造之后配置集成电路。例如，当诸如晶体管的某些内部组件由于制造缺陷而没有指定的电子特性时，可以使用根据本发明的实施例的集成电路的互连层中包括的可调谐电阻的可变电阻的调整以调整内部电压和/或电平以便改善有缺陷的部件。在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。

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