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    • 3. 发明申请
    • Quantum well module with low K crystalline covered substrates
    • 具有低K晶体覆盖基板的量子阱模块
    • US20110100408A1
    • 2011-05-05
    • US12655793
    • 2010-01-06
    • Aleksandr KushchFrederick A. LeavittDaniel KrommenhoekSaeid GhamatyNorbert B. Elsner
    • Aleksandr KushchFrederick A. LeavittDaniel KrommenhoekSaeid GhamatyNorbert B. Elsner
    • H01L35/30H01L21/02H01L35/34
    • H01L35/34C23C14/20C23C14/352C23C14/562F25B2321/023H01L35/22H01L35/32
    • A thermoelectric module comprised of a quantum well thermoelectric material with low thermal conductivity and low electrical resitivity (high conductivity) for producing n-legs and p-legs for thermoelectric modules. These qualities are achieved by fabricating crystalline quantum well super-lattice layers on a substrate material having very low thermal conductivity. Prior to depositing the super-lattice thermoelectric layers the low thermal conductivity substrate is coated with a thin layer of crystalline semi-conductor material, preferably silicon. This greatly improves the thermoelectric quality of the super-lattice quantum well layers. In preferred embodiments the super-lattice layers are about 4 nm to 20 nm thick. In preferred embodiments about 100 to 1000 of these super-lattice layers are deposited on each substrate layer, to provide films of super-lattice layers with thicknesses of in the range of about 0.4 microns to about 20 microns on much thicker substrates. The substrates may be a few microns to a few millimeters thick. The thermoelectric films are then stacked and fabricated into thermoelectric p-legs and n-legs which in turn are fabricated into thermoelectric modules. These layers of quantum well material may in preferred embodiments be separated by much thicker layers of thermal and electrical insulating material such that the volume of insulating material in each leg is at least 20 times larger than the volume of quantum well material.
    • 由热导率低的量子阱热电材料和低电阻率(高导电性)组成的热电模块,用于产生用于热电模块的n型腿和p型腿。 这些质量通过在具有非常低的热导率的衬底材料上制造结晶量子阱超晶格层来实现。 在沉积超晶格热电层之前,低导热性衬底被涂覆有薄的晶体半导体材料,优选硅。 这大大提高了超晶格量子阱层的热电质量。 在优选实施例中,超晶格层约为4nm至20nm厚。 在优选实施例中,在每个衬底层上沉积约100至1000个这些超晶格层,以在更厚的衬底上提供厚度在约0.4微米至约20微米范围内的超晶格层的膜。 衬底可以是几微米到几毫米厚。 然后将热电膜堆叠并制造成热电p支脚和n支脚,其又被制造成热电模块。 量子阱材料的这些层可以在优选的实施方案中由较厚的热和电绝缘材料层隔开,使得每个支脚中的绝缘材料的体积比量子阱材料的体积至少大20倍。