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    • 1. 发明授权
    • Quantifying the read and write margins of memory bit cells
    • 量化存储位单元的读和写余量
    • US08705268B2
    • 2014-04-22
    • US13337902
    • 2011-12-27
    • Myron BuerCarl MonzelYifei Zhang
    • Myron BuerCarl MonzelYifei Zhang
    • G11C11/00G11C29/00G11C5/14G11C8/00
    • G11C11/413G11C8/08G11C11/41G11C11/419G11C29/50G11C2029/1202G11C2029/5002
    • Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.
    • 在筛选老化效应期间,通过在额定工作电压下操作外围电路来防止外围电路故障导致的损耗,同时筛选用于老化效应的存储器阵列。 包括一个或多个存储位单元的集成电路包括改变施加到位单元的电源轨的电压和施加到字线驱动器的电压相对于彼此的电压的电路,以便于改进对读和写余量的屏蔽 。 在正常操作中,字线驱动器和位单元的电源轨标称地相同。 在写裕度测试模式下,字线驱动器的电源轨上的电压低于位单元的电源轨上的电压。 在读取余量测试模式中,字线驱动器的电源轨上的电压高于位单元的电源轨上的电压。
    • 2. 发明申请
    • Quantifying the Read and Write Margins of Memory Bit Cells
    • 量化存储位单元的读和写裕量
    • US20130163357A1
    • 2013-06-27
    • US13337902
    • 2011-12-27
    • Myron BuerCarl MonzelYifei Zhang
    • Myron BuerCarl MonzelYifei Zhang
    • G11C29/00G11C5/14
    • G11C11/413G11C8/08G11C11/41G11C11/419G11C29/50G11C2029/1202G11C2029/5002
    • Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.
    • 在筛选老化效应期间,通过在额定工作电压下操作外围电路来防止外围电路故障导致的损耗,同时筛选用于老化效应的存储器阵列。 包括一个或多个存储位单元的集成电路包括改变施加到位单元的电源轨的电压和施加到字线驱动器的电压相对于彼此的电压的电路,以便于改进对读和写余量的屏蔽 。 在正常操作中,字线驱动器和位单元的电源轨标称地相同。 在写裕度测试模式下,字线驱动器的电源轨上的电压低于位单元的电源轨上的电压。 在读取余量测试模式中,字线驱动器的电源轨上的电压高于位单元的电源轨上的电压。
    • 3. 发明授权
    • Iterative decoding systems using noise-biasing
    • 使用噪声偏置的迭代解码系统
    • US08745468B1
    • 2014-06-03
    • US12357200
    • 2009-01-21
    • Yifei ZhangNedeljko VarnicaGregory Burd
    • Yifei ZhangNedeljko VarnicaGregory Burd
    • H03M13/00
    • G06F11/1004H03M13/1102H03M13/1111H03M13/1117H03M13/2951H03M13/3723H03M13/6331H03M13/6508H03M13/658
    • Systems, methods, and apparatus are provided for improving the iterative decoding performance of a decoder, for example, as used in a wireless communications receiver or in a data retrieval unit. A decoding technique may receive and process a set of channel samples using an iterative decoder. If the iterative decoder output indicates a decoding failure, noise samples may be combined with the received channel samples to create biased channel samples. Noise samples may be generated using a pseudo-random noise generator and/or by using signals already present in the communications receiver or data retrieval unit. The biased channel samples may be provided to the iterative decoder and the iterative decoder may re-run using the biased channel samples.
    • 提供了系统,方法和装置,用于改进解码器的迭代解码性能,例如,如在无线通信接收机或数据检索单元中所使用的那样。 解码技术可以使用迭代解码器来接收和处理一组信道样本。 如果迭代解码器输出指示解码失败,则可以将噪声样本与接收到的信道样本组合以产生偏置信道样本。 可以使用伪随机噪声发生器和/或通过使用已经存在于通信接收器或数据检索单元中的信号来产生噪声样本。 可以将偏置的信道样本提供给迭代解码器,并且迭代解码器可以使用偏置信道样本重新运行。
    • 4. 发明授权
    • Name detection
    • 名称检测
    • US08478787B2
    • 2013-07-02
    • US12746465
    • 2007-12-06
    • Jun WuHui XuYifei Zhang
    • Jun WuHui XuYifei Zhang
    • G06F17/30
    • G06F17/278
    • Methods, systems, and apparatus, including computer programs encoded on computer storage media, for name detection. A method includes generating a raw name detection model using a collection of family names and an annotated corpus including a collection of n-grams. The method includes applying the raw name detection model to a collection of semi-structured data to form annotated semi-structured data identifying n-grams identifying names and n-grams not identifying names and applying the raw name detection model to a large unannotated corpus to form a large annotated corpus data identifying n-grams of the large unannotated corpus identifying names and n-grams not identifying names. The method includes generating a name detection model, including deriving a name model using the annotated semi-structured data identifying names and the large annotated corpus data identifying names, deriving a not-name model using the semi-structured data not identifying names, and deriving a language model using the large annotated corpus.
    • 方法,系统和装置,包括在计算机存储介质上编码的计算机程序,用于名称检测。 一种方法包括使用族名集合和包括n-gram集合的注释语料库来生成原始名称检测模型。 该方法包括将原始名称检测模型应用于半结构化数据的集合,以形成标识识别名称的n-gram和不识别名称的n-gram的注释半结构化数据,并将原始名称检测模型应用于大型未注释语料库 形成一个大的注释语料库数据,用于识别大型未注释语料库识别名称的n-gram和不识别姓名的n-gram。 该方法包括生成名称检测模型,包括使用标识名称的注释半结构化数据和识别名称的大型注释语料库数据来导出名称模型,使用不标识姓名的半结构化数据导出非名称模型,以及导出 一种使用大型注释语料库的语言模型。
    • 9. 发明授权
    • SRAM with read assist
    • SRAM具有读取辅助功能
    • US07366006B2
    • 2008-04-29
    • US11401679
    • 2006-04-11
    • Yifei Zhang
    • Yifei Zhang
    • G11C11/00
    • G11C11/419G11C11/4125
    • A Static Random Access Memory (SRAM) matrix with a read assist is described. The read assist reduces the probability associated with an SRAM matrix becoming upset by a radiation event. Each SRAM cell within the SRAM matrix includes an active delay for increasing Single Event Upset (SEU) tolerance. The described SRAM matrix also includes a read assist coupled to each column of the SRAM matrix. The read assists store values associated with a row of SRAM cells, one SRAM cell of which is to be written to. If a radiation event occurs on any of the SRAM cells not being written to, the read assist restores an original value associated with the upset SRAM cell.
    • 描述了具有读辅助的静态随机存取存储器(SRAM)矩阵。 读取辅助减少与由辐射事件扰乱的SRAM矩阵相关联的概率。 SRAM矩阵中的每个SRAM单元包括用于增加单次事件颠簸(SEU)容差的有效延迟。 所描述的SRAM矩阵还包括耦合到SRAM矩阵的每列的读辅助。 读取辅助存储与一行SRAM单元相关联的值,其中一个SRAM单元将被写入。 如果在未写入的任何SRAM单元上发生辐射事件,则读取辅助恢复与不稳定SRAM单元相关联的原始值。