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    • 1. 发明授权
    • Optical receiver with a calibration mode
    • 具有校准模式的光接收机
    • US08238761B2
    • 2012-08-07
    • US12633934
    • 2009-12-09
    • Frankie Y. LiuDinesh D. PatilRonald HoElad Alon
    • Frankie Y. LiuDinesh D. PatilRonald HoElad Alon
    • H04B10/06
    • H04B10/6911
    • An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.
    • 描述了光接收机。 该光接收器包括数字反馈电路,该数字反馈电路偏置接收光信号的前端电路,使得由前端电路输出的模拟电信号相对于对应于数字的判定阈值的参考电压进行校准 切片机在光接收机。 特别地,在校准模式期间,反馈电路可以确定并存储校准相对于参考电压的模拟电信号的校准值。 然后,在正常操作模式期间,反馈电路可输出对应于存储的校准值的电流,该校准值指定前端电路的偏置点。
    • 2. 发明申请
    • OPTICAL RECEIVER WITH A CALIBRATION MODE
    • 具有校准模式的光接收器
    • US20110135315A1
    • 2011-06-09
    • US12633934
    • 2009-12-09
    • Frankie Y. LiuDinesh D. PatilRonald HoElad Alon
    • Frankie Y. LiuDinesh D. PatilRonald HoElad Alon
    • H04B10/00H04B10/06
    • H04B10/6911
    • An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.
    • 描述了光接收机。 该光接收器包括数字反馈电路,该数字反馈电路偏置接收光信号的前端电路,使得由前端电路输出的模拟电信号相对于对应于数字的判定阈值的参考电压进行校准 切片机在光接收机。 特别地,在校准模式期间,反馈电路可以确定并存储校准相对于参考电压的模拟电信号的校准值。 然后,在正常操作模式期间,反馈电路可输出对应于存储的校准值的电流,该校准值指定前端电路的偏置点。
    • 7. 发明授权
    • Apparatus and method for a digital delay locked loop
    • 数字延迟锁定环的装置和方法
    • US06642760B1
    • 2003-11-04
    • US10112963
    • 2002-03-29
    • Elad AlonScott Best
    • Elad AlonScott Best
    • H03L706
    • H03K3/037H03K3/0375H03L7/0802H03L7/0814
    • A circuit and method is shown for digital control of delay lines in a delay locked loop (DLL) system. A pair of multiplexors (MUXes) is used to select output taps from a pair of complementary delay lines that delay a reference clock signal in order to lock onto a received clock signal. An output tap from one delay line is used to produce a rising edge in an output clock signal while a corresponding tap in the complementary delay line is used to produce a falling edge in the output signal in order to correct for distortion. The MUXes are controlled based on a phase difference detected between the received clock signal and a feedback clock corresponding to the output clock signal. Another aspect of the present invention provides for generation of a quadrature clock by interpolating between the rising and falling edges selected for the output clock signal. Still another aspect of the present invention provides for selectively disabling unused elements of the delay lines to reduce power consumption.
    • 示出了延迟锁定环(DLL)系统中的延迟线的数字控制的电路和方法。 一对多路复用器(MUX)用于从延迟参考时钟信号的一对互补延迟线中选择输出抽头,以便锁定到所接收的时钟信号上。 来自一个延迟线的输出抽头用于产生输出时钟信号中的上升沿,而互补延迟线中的相应抽头用于在输出信号中产生下降沿以便校正失真。 基于在接收的时钟信号和对应于输出时钟信号的反馈时钟之间检测到的相位差来控制MUX。 本发明的另一方面提供了通过在为输出时钟信号选择的上升沿和下降沿之间进行内插来产生正交时钟。 本发明的另一方面提供了选择性地禁用延迟线的未使用元件以降低功耗。