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1. 发明授权

US5790394A Dual AC power supply input module 失效
标题翻译：双交流电源输入模块
公开(公告)号：US5790394A
公开(公告)日：1998-08-04
申请号：US767761
申请日：1996-12-17
申请人： Frank W. Cabaniss , Gene F. Young , James S. Kluttz
发明人： Frank W. Cabaniss , Gene F. Young , James S. Kluttz
IPC分类号： H02J1/10 , H02J3/38 , H02M7/17 , H02M7/155
CPC分类号： H02J3/38 , H02J1/108 , H02M7/17 , Y10T307/707
摘要： A dual AC input module providing AC line isolation of different phases without the use of relay control. Power supply load is supported through two AC line feeds, each feed being connected through a bridge rectifier to a common bulk DC power supply backplane. The parallel configuration of AC line feeds and bridge rectifiers eliminates the need for relay control logic to open relays and isolate a failed primary AC line feed prior to closing relays to connect a second AC feed to the power supply, as required with previous dual AC input module designs to isolate different line feeds of different phases.
摘要翻译：双交流输入模块，不使用继电器控制，提供不同相的交流线路隔离。通过两个交流线路馈电支持电源负载，每个馈电通过桥式整流器连接到通用的大容量直流电源背板。交流线路馈电和桥式整流器的并联配置不需要继电器控制逻辑来打开继电器并隔离故障的主要交流线路馈电，在关闭继电器之前将第二个交流电源连接到电源，如以前的双交流输入模块设计来隔离不同阶段的不同线路馈送。

2. 发明授权

US5860120A Directory-based coherency system using two bits to maintain coherency on a dual ported memory system 失效
标题翻译：基于目录的一致性系统，使用两个比特来保持双端口存储系统上的一致性
公开(公告)号：US5860120A
公开(公告)日：1999-01-12
申请号：US763702
申请日：1996-12-09
申请人： Gene F. Young , Roy M. Stevens , Larry C. James
发明人： Gene F. Young , Roy M. Stevens , Larry C. James
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： An improved directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a dual ported system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port (PORT A) of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port (PORT B) of the system memory. Cache coherency is maintained through the use of memory line state information saved with each line of memory within the system memory and data cache memories. The system memory contains a system memory line state for each line of memory saved within the system memory, the system memory line state being any one of the group: SHARED PORT A, SHARED BOTH, OWNED PORT A and OWNED PORT B. Each one of these states is represented by a different two bit code saved with each line of memory in system memory. Additionally, each data cache memory contains a data cache memory line state for each line of memory saved within the data cache memory, the data cache memory line state being any one of the group: MODIFIED, EXCLUSIVE, SHARED, or INVALID.
摘要翻译：用于多处理器计算机系统的改进的基于目录的高速缓存一致性存储器系统。存储器系统包括由计算机系统内的多个处理器共享的双端口系统存储器; 多个数据高速缓存存储器，与每个处理器相关联的至少一个数据高速缓冲存储器; 以及第一和第二存储器总线，第一存储器总线将处理器的第一子集和相关联的数据高速缓冲存储器连接到系统存储器的第一端口（端口A），以及连接处理器的第二子集和相关联的数据高速缓存的第二存储器总线存储到系统存储器的第二个端口（端口B）。通过使用与系统存储器和数据高速缓冲存储器内的每行存储器一起存储的存储器线路状态信息来维持高速缓存一致性。系统内存包含系统内存中保存的每行内存的系统内存线状态，系统内存线状态为组中的任何一个：共享端口A，共享端口A，已连接端口A和已连接端口B.每个这些状态由系统存储器中的每行存储器保存的不同的两个位代码表示。此外，每个数据高速缓冲存储器包含保存在数据高速缓冲存储器内的每行存储器的数据高速缓冲存储器线路状态，数据高速缓冲存储器线路状态是以下任一组：MODIFIED，EXCLUSIVE，SHARED或INVALID。

3. 发明授权

US5359715A Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces 失效
标题翻译：具有多个处理器，多个系统总线和多个I / O总线的计算机系统架构，通过多个端口接口连接
公开(公告)号：US5359715A
公开(公告)日：1994-10-25
申请号：US760786
申请日：1991-09-16
申请人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
发明人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
IPC分类号： G06F15/16 , G06F13/24 , G06F13/36 , G06F15/177 , G06F13/00
CPC分类号： G06F13/24
摘要： Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.
摘要翻译：多处理器系统被配置为包括至少两个系统或存储器总线，其中至少两个处理器耦合到每个系统总线，以及耦合到系统总线的至少两个I / O总线，以提供多个扩展槽，为每个I / O总线以单个系统总线负载为代价的系统的相应数量的I / O总线代理。系统和I / O总线中的每一个被独立地仲裁以定义用于本发明的多个处理器系统的解耦总线系统。用于系统的主存储器由至少两个存储器交错组成，每个存储器交错可以通过系统总线同时访问。每个I / O总线通过I / O接口电路连接到系统总线，I / O接口电路缓冲写入主存储器的数据或由I / O总线代理器读取存储器交错的数据。

4. 发明授权

US5809536A Method for reducing the number of coherency cycles within a directory-based cache coherency memory system uitilizing a memory state cache 失效
标题翻译：用于减少基于目录的高速缓存一致性存储器系统内的一致性循环次数的方法来利用存储器状态高速缓存
公开(公告)号：US5809536A
公开(公告)日：1998-09-15
申请号：US763703
申请日：1996-12-09
申请人： Gene F. Young , Roy M. Stevens , Larry C. James
发明人： Gene F. Young , Roy M. Stevens , Larry C. James
IPC分类号： G06F12/08 , G06F12/14
CPC分类号： G06F12/082
摘要： An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories. The method for performing state cache line replacement operations includes the steps of: establishing a default system memory line state of SHARED for lines of memory represented in said state cache memory; reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory; and performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED. Since most lines of memory are in a shared state prior to replacement, setting the default state to a shared state, rather than a uncached state, reduces the number of invalidate coherency operations which must be performed during state cache line replacements.
摘要翻译：一种用于在多处理器计算机系统中执行状态高速缓存行替换操作的改进方法，包括多个数据高速缓冲存储器，共享系统存储器，状态高速缓冲存储器以及采用基于集中式/分布式基于目录的高速缓存一致性系统，用于维持共享系统存储器内的存储器和多个数据高速缓冲存储器。执行状态高速缓存行替换操作的方法包括以下步骤：为在所述状态高速缓存存储器中表示的存储器行建立默认系统存储器线状态; 在替换所述先前存储的状态高速缓存条目之前读取先前存储的状态高速缓存条目的系统存储器线路状态，所述先前存储的状态高速缓存条目与存储在所述共享存储器中的存储器行相关联，以及至少一个数据高速缓冲存储器 ; 以及如果用于所述先前存储的所述系统存储器线状态，则执行舍弃操作以更新所述共享存储器内的存储器行并且将包含所述存储器行的每个数据高速缓冲存储器中的数据高速缓冲存储器线状态分配给所述存储器的所述行存储器状态缓存条目为OWNED。由于大多数存储器行在替换之前处于共享状态，因此将默认状态设置为共享状态而不是未缓存状态可以减少在状态高速缓存行替换期间必须执行的无效一致性操作的数量。

5. 发明授权

US5454082A System for preventing an unselected controller from transferring data via a first bus while concurrently permitting it to transfer data via a second bus 失效
标题翻译：用于防止未选择的控制器经由第一总线传送数据同时允许其经由第二总线传送数据的系统
公开(公告)号：US5454082A
公开(公告)日：1995-09-26
申请号：US175157
申请日：1992-11-12
申请人： Craig A. Walrath , Jimmy D. Pike , Gene F. Young
发明人： Craig A. Walrath , Jimmy D. Pike , Gene F. Young
IPC分类号： G06F13/362 , G06F13/40 , G06F13/36
CPC分类号： G06F13/362 , G06F13/4036
摘要： An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.
摘要翻译：用于计算机系统的交错锁定装置确保在所选择的智能控制器和所选择的存储器交错之间的选定总线上的数据传输操作的原子性，而不干扰在未选择的智能控制器与未选择的存储器交错之间的未选择总线上的数据传输。所选择的智能控制器通过所选择的总线发出的交错锁定信号被检测并且仅当所述交错锁定信号被断言时，仅阻止所选总线上的未选择的智能控制器执行总线周期。

6. 发明授权

US5269005A Method and apparatus for transferring data within a computer system 失效
标题翻译：用于在计算机系统内传送数据的方法和装置
公开(公告)号：US5269005A
公开(公告)日：1993-12-07
申请号：US761185
申请日：1991-09-17
申请人： Thomas F. Heil , Edward A. McDonald , Gene F. Young
发明人： Thomas F. Heil , Edward A. McDonald , Gene F. Young
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit. In response to the retry signal, the processor is taken off the system bus and not allowed to regain the system bus until the buffered data is written to main memory. A bus busy signal is raised and will not be lowered until the data is written to main memory. When the busy signal is lowered, the processor regains the system bus and receives an interrupt vector from the interrupt controller. I/O bus ownership is locked until the interrupted processor has received an interrupt vector and the IAK cycle is complete. If no buffered data remains in the interface circuit, no retry signal is generated. The interrupt controller waits a predefined period of time for a retry signal and if none is detected, the interrupt controller issues an appropriate interrupt vector to complete the IAK cycle. For multiple I/O buses, preferably only one interface circuit retries processors issuing IAK cycles.
摘要翻译：在处理系统中，对中断确认周期的任何响应都被推迟，直到将从子系统I / O总线上的代理写入缓冲数据传送到系统的主存储器得到保证。为了加快系统运行，由I / O总线上的代理程序写入主存的数据被缓存在接口电路中。一旦数据被缓冲，I / O总线代理被释放并中断系统总线上的处理器，指示完成数据写入。使用紧密耦合的中断控制器，以便代理不需要拥有I / O或系统总线来产生中断。中断的处理器在系统总线上发出中断确认（IAK）周期，以从中断控制器接收中断向量。接口电路识别IAK周期，并且如果缓冲数据保留在接口电路中，则为处理器生成重试信号。响应于重试信号，处理器从系统总线中取出，不允许重新获得系统总线，直到缓冲的数据被写入主存储器。总线忙信号升高，直到数据写入主存储器才会降低。当忙信号降低时，处理器恢复系统总线并从中断控制器接收中断向量。 I / O总线所有权被锁定，直到中断处理器收到中断向量并且IAK周期完成。如果接口电路中没有缓冲的数据，则不会产生重试信号。中断控制器等待重试信号的预定义时间段，如果没有检测到，中断控制器发出适当的中断向量来完成IAK周期。对于多个I / O总线，最好只有一个接口电路重试发出IAK周期的处理器。

7. 发明授权

US5991819A Dual-ported memory controller which maintains cache coherency using a memory line status table 失效
标题翻译：双端口存储器控制器，其使用存储器线状态表维护高速缓存一致性
公开(公告)号：US5991819A
公开(公告)日：1999-11-23
申请号：US760126
申请日：1996-12-03
申请人： Gene F. Young
发明人： Gene F. Young
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1663
摘要： A symmetric multiprocessor system constructed from industry standard commodity components together with an advanced dual-ported memory controller. The multiprocessor system comprises a processor bus; up to four Intel Pentium.RTM. Pro processors connected to the processor bus; an I/O bus; a system memory; and a dual-ported memory controller connected to the system memory, the dual ported memory controller having a first port connected to the processor bus to manage processor to system memory transactions and a second port connected to the I/O bus to manage I/O transactions. Furthermore, two such systems can be connected together through a common I/O bus, thereby creating an eight-processor Pentium.RTM. Pro processor SMP system.
摘要翻译：一种由行业标准商品组件构成的对称多处理器系统以及高级双端口存储器控制器。多处理器系统包括处理器总线; 连接到处理器总线的四个Intel Pentium TM Pro处理器; 一个I / O总线; 系统内存和连接到系统存储器的双端口存储器控制器，双端口存储器控制器具有连接到处理器总线的第一端口以管理处理器到系统存储器事务，以及连接到I / O总线的第二端口以管理I / O 交易。此外，两个这样的系统可以通过公共I / O总线连接在一起，从而创建一个八处理器Pentium TM Pro处理器SMP系统。

8. 发明授权

US5848434A Method and apparatus for caching state information within a directory-based coherency memory system 失效
标题翻译：用于在基于目录的一致性存储器系统内缓存状态信息的方法和装置
公开(公告)号：US5848434A
公开(公告)日：1998-12-08
申请号：US762636
申请日：1996-12-09
申请人： Gene F. Young , Roy M. Stevens , Larry C. James
发明人： Gene F. Young , Roy M. Stevens , Larry C. James
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F12/0813 , G06F12/082
摘要： A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time. The state cache can be a direct mapped cache wherein state information for an associated line of memory is stored within the state cache together with a tag field being a first portion of the address of the associated line of memory, and indexed within the state cache by the remaining portion of the address.
摘要翻译：用于多处理器计算机系统的基于目录的高速缓存一致性存储器系统。存储器系统包括由计算机系统内的多个处理器共享的系统存储器; 多个数据高速缓存存储器，与每个处理器相关联的至少一个数据高速缓冲存储器; 将系统存储器与多个数据高速缓冲存储器和处理器互连的总线系统，以及与共享系统存储器相关联的状态高速缓冲存储器，用于存储识别系统存储器和多个数据高速缓冲存储器内的哪里的存储器线路状态信息一行内存的最新副本驻留。状态高速缓冲存储器的大小被确定为仅存储系统存储器中包括的存储器线路的一部分的状态信息，例如，包含在系统存储器中的存储器线路的十六分之一，认识到很少使用所有系统存储器（高速缓存）在任何一个时间状态缓存可以是直接映射高速缓存，其中相关联的存储器行的状态信息与作为相关行存储器的地址的第一部分的标签字段一起存储在状态高速缓存中，并且通过地址的剩余部分。

9. 发明授权

US6078997A Directory-based coherency system for maintaining coherency in a dual-ported memory system 失效
标题翻译：基于目录的一致性系统，用于在双端口存储器系统中维持一致性
公开(公告)号：US6078997A
公开(公告)日：2000-06-20
申请号：US762618
申请日：1996-12-09
申请人： Gene F. Young , Roy M. Stevens , Larry C. James
发明人： Gene F. Young , Roy M. Stevens , Larry C. James
IPC分类号： G06F12/08
CPC分类号： G06F12/0826
摘要： Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are "Owned" and "Unowned." The state of the bit is used to filter the number of cycles required to maintain coherency. The bits are stored within the system memory.
摘要翻译：每行系统存储器使用一位以保持双端口存储器系统中的一致性的方法和装置。这些位的状态是“拥有”和“未知”。该位的状态用于过滤维护一致性所需的周期数。这些位被存储在系统存储器中。

10. 发明授权

US5418914A Retry scheme for controlling transactions between two busses 失效
标题翻译：用于控制两台总线之间的交易的重试方案
公开(公告)号：US5418914A
公开(公告)日：1995-05-23
申请号：US143393
申请日：1993-10-25
申请人： Thomas F. Heil , Edward A. McDonald , Gene F. Young , Craig A. Walrath , James M. Ottinger , Marti D. Miller
发明人： Thomas F. Heil , Edward A. McDonald , Gene F. Young , Craig A. Walrath , James M. Ottinger , Marti D. Miller
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F13/362
摘要： A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.
摘要翻译：一种用于优化在计算机系统中使用第一总线的重试方案，该计算机系统包括通过第一总线连接到接口电路和第二总线的多个总线主机。接口电路包括当第二总线处于忙状态时产生忙信号的逻辑和当第二总线处于忙状态时当总线主机寻址接口电路时产生重试信号的逻辑。每个总线主机包括用于在从接口电路接收到重试信号时接收重试信号和放弃公共总线的控制的逻辑。总线仲裁器包括用于接收忙信号的逻辑，并且阻止任何总线主机寻求访问第二总线参与用于控制公共第一总线的仲裁，直到忙信号被否定为止。因此，在忙信号期间，第一总线可以由不需要访问共享资源的任何总线主控器来控制。在否定忙碌信号后，所有巴士主人将被允许竞争总线的所有权。

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