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1. 发明申请

US20060193395A1 Combined alignment scrambler function for elastic interface 失效
标题翻译：组合对齐扰频器功能用于弹性界面
公开(公告)号：US20060193395A1
公开(公告)日：2006-08-31
申请号：US11055817
申请日：2005-02-11
申请人： Frank Ferraiolo , Robert Reese , Michael Spear
发明人： Frank Ferraiolo , Robert Reese , Michael Spear
IPC分类号： H04L5/12
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/044 , H04L7/046 , H04L7/10
摘要： An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.
摘要翻译：公开了一种用于在弹性接口上接收的用于去偏斜数据比特的接口对准模式。接口对齐模式是“忙”，因为它具有大量的逻辑状态转换。忙接口对准模式可用于加扰和解扰操作数据。接口对准模式具有用于确定数据位的第一数据节拍位置的唯一定时序列。

2. 发明申请

US20060181914A1 Alignment mode selection mechanism for elastic interface 失效
标题翻译：弹性界面对准模式选择机构
公开(公告)号：US20060181914A1
公开(公告)日：2006-08-17
申请号：US11055841
申请日：2005-02-11
申请人： Frank Ferraiolo , Gary Peterson , Robert Reese
发明人： Frank Ferraiolo , Gary Peterson , Robert Reese
IPC分类号： G11C19/00
CPC分类号： G11C19/287 , G06F5/10 , G06F2205/104
摘要： Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock edges, on falling clock edges if the data was sent on falling clock edges, or on the nearest clock edge if minimum latency is desired. Alternatively, data bits can be delayed by one or more bit times before loading into FIFO latches to reduce the elastic interface system's sensitivity to drift. The present invention permits a user to trade off factors related to for latency, drift, and skew by choosing among different alignment modes in an elastic interface system.
摘要翻译：公开了用于在弹性界面系统中对准接收数据位的方法和装置。根据选择的几种对准模式中的哪一种，如果数据在上升时钟沿发送，则数据位可以在上升时钟沿加载到FIFO锁存器中，如果数据在下降时钟沿发送，则在下降时钟沿如果需要最小延迟，则为最近的时钟沿。或者，数据位可以在加载到FIFO锁存器之前延迟一个或多个位时间，以减少弹性接口系统对漂移的敏感度。本发明允许用户通过在弹性接口系统中的不同对准模式之间进行选择来折衷与延迟，漂移和偏斜相关的因素。

3. 发明申请

US20080074998A1 SELF-HEALING CHIP-TO-CHIP INTERFACE 有权
标题翻译：自我加工芯片到芯片接口
公开(公告)号：US20080074998A1
公开(公告)日：2008-03-27
申请号：US11948620
申请日：2007-11-30
申请人： WIREN BECKER , Daniel Dreps , Frank Ferraiolo , Anand Haridass , Robert Reese
发明人： WIREN BECKER , Daniel Dreps , Frank Ferraiolo , Anand Haridass , Robert Reese
IPC分类号： G01R31/08 , G06F11/00
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

4. 发明申请

US20060182215A1 Dynamic recalibration mechanism for elastic interface 失效
标题翻译：弹性界面的动态重新校准机制
公开(公告)号：US20060182215A1
公开(公告)日：2006-08-17
申请号：US11055865
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
发明人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
IPC分类号： H04L7/00
CPC分类号： H04L7/005 , G11C19/287 , H03K5/133 , H03K2005/00058 , H04L7/0338
摘要： A method and apparatus for de-skewing and aligning digital data received over and elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wraparound eye tracking.
摘要翻译：公开了一种用于使接收到的数字数据进行偏斜和对准的弹性接口总线的方法和装置。在接收到数据后，通过可编程延迟线发送。在可编程延迟线中，数据在数据眼图中的三个点进行采样。动态调整三个采样点，以最大化数据眼图的覆盖范围。在调整采样点以最佳地覆盖数据的眼图时，延迟数据从备用采样器采样，以防止在主采样器中的延迟调整时从功能采样器采样。在更换功能采样器的采样点时，从备用采样器进行采样可以减少在采样参数变化时采样功能采样器可能发生的毛刺。该方法和装置允许替代眼睛跟踪和环绕眼睛跟踪。

5. 发明申请

US20060181320A1 Circuit for optimizing the duty cycle of a received clock transmitted over a transmission line 审中-公开
标题翻译：用于优化通过传输线传输的接收时钟的占空比的电路
公开(公告)号：US20060181320A1
公开(公告)日：2006-08-17
申请号：US11055851
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
发明人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
IPC分类号： H03L7/06
CPC分类号： H04L7/033 , H03L7/0814 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L25/0272
摘要： Data signals are transmitted over transmission lines in groups to receivers in a receiving IC. Each group of data signals has a differential clock used in synchronizing and detecting the data signals. The data signal eye windows vary with timing jitter in the data signals relative to the clock edges and the asymmetry in a compensated clock signal detected from the differential clock using a duty cycle adjustment circuit. Error detection determines if the clock asymmetry is affecting the eye window of the data signals. Control signals selectively adjust the gain of differential stages generating the compensated clock to modify the duty cycle of the compensated clock. The eye window of the data signals are monitored and used as feedback to servo the control signals to optimize the duty cycle of the compensated clock signal for sampling the data signals.
摘要翻译：数据信号通过传输线组传送到接收IC中的接收器。每组数据信号具有用于同步和检测数据信号的差分时钟。数据信号眼窗随数据信号相对于时钟边缘的定时抖动和使用占空比调整电路从差分时钟检测到的补偿时钟信号的不对称性而变化。错误检测确定时钟不对称是否影响数据信号的眼睛窗口。控制信号选择性地调节产生补偿时钟的差分级的增益，以修改补偿时钟的占空比。数据信号的眼窗被监视并用作伺服控制信号的反馈，以优化用于采样数据信号的经补偿的时钟信号的占空比。

6. 发明申请

US20060181303A1 Data receiver with a programmable reference voltage to optimize timing jitter 失效
标题翻译：具有可编程参考电压的数据接收器，以优化定时抖动
公开(公告)号：US20060181303A1
公开(公告)日：2006-08-17
申请号：US11055805
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
发明人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
IPC分类号： H03K19/003
CPC分类号： H04L25/0292 , G06F13/4072 , H04L7/0033 , H04L25/0272
摘要： Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.
摘要翻译：伪差分驱动器和接收器用于在两个或更多个IC芯片之间传送数据信号。使用可编程延迟电路对数据路径进行对齐，以使每个数据路径发生偏移。可编程参考发生器用于产生一个或一组接收机使用的参考电压，以检测数据信号。参考电压可以使用粗调以及精细的数字控制电压增量进行调节。测试信号从驱动器发送到接收器，并且参考电压在其可调节范围内使用粗略和精细调节控制来改变，而电路确定测试信号的连续转换时的检测定时抖动的量度。将参考电压的操作值设定为检测定时抖动确定为最小的值。

7. 发明申请

US20060176096A1 Power supply insensitive delay element 审中-公开
标题翻译：电源不敏感延迟元件
公开(公告)号：US20060176096A1
公开(公告)日：2006-08-10
申请号：US11056798
申请日：2005-02-10
申请人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Robert Reese , Hector Saenz , Michael Sperling
发明人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Robert Reese , Hector Saenz , Michael Sperling
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00039 , H03K2005/0013
摘要： A power supply voltage insensitive delay element is provided that enables a digital signal to be delayed without variation due to power supply vulnerabilities. Current is limited through the transistors of the delay element using bias voltages produced by a bias voltage generator coupled to the delay element. The bias voltage generator and the delay element are included in a delay line which facilitates the providing of a delay that is insensitive to voltage fluctuations.
摘要翻译：提供了电源电压不敏感延迟元件，其使数字信号由于电源漏洞而被延迟而没有变化。使用由耦合到延迟元件的偏置电压发生器产生的偏置电压，延迟元件的晶体管限制电流。偏置电压发生器和延迟元件包括在延迟线中，这有助于提供对电压波动不敏感的延迟。

8. 发明申请

US20060184817A1 Elastic interface de-skew mechanism 有权
标题翻译：弹性界面去歪斜机制
公开(公告)号：US20060184817A1
公开(公告)日：2006-08-17
申请号：US11055866
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
发明人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
IPC分类号： G06F1/04
CPC分类号： G06F5/06 , G06F1/10
摘要： A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.
摘要翻译：用于在弹性界面上在两个芯片之间发送的数据位的偏斜和对准的机制。在弹性接口的接收端，时钟/数据组内的每个数据位的眼睛被延迟小于一点时间，以使眼睛与接收到的时钟信号的最近的时钟沿对齐。除了将各个数据位的眼睛与最近的时钟边沿对齐之外，还使用IAP模式来确定从每个数据位排列各个数据节拍所需的进一步延迟量。如果数据位的数据跳转不对齐，除了最慢的数据跳转之外，除了所有位的数据跳转之外，都会被延迟。使用采样锁存器实现额外的延迟，导致延迟信号抖动较小。由于具有较少的抖动，所接收的，去偏斜的和对准的时钟/数据组可以以增加的频率转发到接收芯片的操作部分。

9. 发明申请

US20060072476A1 Delivery of streaming media 有权
公开(公告)号：US20060072476A1
公开(公告)日：2006-04-06
申请号：US11291861
申请日：2005-11-30
申请人： Sudheer Sirivara , Jeffrey McVeigh , Robert Reese , Gianni Ferrise , Phillip Austin , Ram Rao , Shobhana Subramanian
发明人： Sudheer Sirivara , Jeffrey McVeigh , Robert Reese , Gianni Ferrise , Phillip Austin , Ram Rao , Shobhana Subramanian
IPC分类号： H04L12/26
CPC分类号： H04N7/173 , H04L43/00 , H04L43/0829 , H04L43/0852 , H04L43/087 , H04N17/004 , H04N21/23418 , H04N21/4331 , H04N21/44008 , H04N21/44209 , H04N21/6125 , H04N21/6131
摘要： A method for evaluating an end-user's subjective assessment of streaming media quality includes obtaining reference data characterizing the media stream, and obtaining altered data characterizing the media stream after the media stream has traversed a channel that includes a network. An objective measure of the QOS of the media stream is then determined by comparing the reference data and the altered data.

10. 发明申请

US20060033646A1 Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry 有权
公开(公告)号：US20060033646A1
公开(公告)日：2006-02-16
申请号：US10896504
申请日：2004-07-22
申请人： Daniel Dreps , Robert Reese , Hector Saenz
发明人： Daniel Dreps , Robert Reese , Hector Saenz
IPC分类号： H03M7/00
CPC分类号： H04L25/03866 , H04L7/0008
摘要： Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.

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