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1. 发明授权

US5274282A Monostabilized dynamic programmable logic array in CMOS technology 失效
标题翻译： CMOS技术中的单稳态动态可编程逻辑阵列
公开(公告)号：US5274282A
公开(公告)日：1993-12-28
申请号：US970609
申请日：1992-10-30
申请人： Flavio Scarra , Siro M. Morganti , Giuseppe Meroni
发明人： Flavio Scarra , Siro M. Morganti , Giuseppe Meroni
IPC分类号： H03K19/177 , H03K19/173 , H03K19/094
CPC分类号： H03K19/17716
摘要： The circuit includes an input register (RI); an output register (RU); an AND plane; and an OR plane. The AND plane has vertical lines (Y), which are controlled by the input register, and horizontal lines (L), which include transistors (TA) arranged in series and controlled by respective vertical lines. The horizontal lines are connected to ground by normally-off transistors (TV) and to the power supply by normally-on transistors (TP). These transistors (TV, TP) are controlled by a first clock signal (CK1.about.). The OR plane has horizontal lines (S) and vertical lines (U). The vertical lines (U) of the OR plane contain normally-off transistors (TO) which are controlled by respective horizontal lines of the OR plane. Horizontal lines of the AND plane and horizontal lines of the OR plane are connected by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and ground. In each pair, the normally-on transistor is controlled by a horizontal line of the AND plane, and the normally-off transistor is controlled by a second clock signal (CK2). A horizontal line of the OR plane is connected to the node between the pair. The vertical lines of the OR plane are connected to the power supply by respective transistors (TR), which are controlled by a third clock signal (CK2.about.), and to the output register by pass transistors (P), which are controlled by a fourth clock signal (CK3.about.).
摘要翻译：该电路包括一个输入寄存器（RI）; 输出寄存器（RU）; 一个AND平面; 和OR平面。 AND平面具有由输入寄存器控制的垂直线（Y）和包括串联布置并由相应垂直线控制的晶体管（TA）的水平线（L）。水平线通过常闭晶体管（TV）连接到地，并通过常开晶体管（TP）连接到电源。这些晶体管（TV，TP）由第一时钟信号（CK1 DIFFERENCE）控制。 OR平面具有水平线（S）和垂直线（U）。 OR平面的垂直线（U）包含由OR平面的相应水平线控制的常闭晶体管（TO）。 AND平面的水平线和OR平面的水平线通过串联布置在电源和地之间的各对正常导通晶体管（TB）和常关断晶体管（TC）连接。在每对中，常通晶体管由AND平面的水平线控制，而常闭晶体管由第二时钟信号（CK2）控制。 OR平面的水平线连接到该对之间的节点。 OR平面的垂直线通过由第三时钟信号（CK2 DIFFERENCE）控制的相应晶体管（TR）连接到电源，并且由通过晶体管（P）控制的输出寄存器第四个时钟信号（CK3 DIFFERENCE）。

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