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    • 1. 发明授权
    • Braking band, a ventilated disk-brake disk, and a core box for the production of a disk-brake disk core
    • 制动带,通风盘式制动盘和用于生产盘式制动盘芯的核心箱
    • US07690484B2
    • 2010-04-06
    • US10473822
    • 2002-04-05
    • Leone ObertiLorenzo CavagnaGiuseppe Meroni
    • Leone ObertiLorenzo CavagnaGiuseppe Meroni
    • F16D65/12
    • B22C7/06B22C9/10B22C9/28F16D65/12F16D2065/1328F16D2200/0013F16D2250/0007
    • A braking band with a remarkable capacity for improved cooling, for use in disk-brake disks, comprises two plates coaxial with an axis, facing one another, and spaced apart to form a space in which an air-flow takes place from the axis towards the outer side of the band, the plates having facing surfaces from which pillar-like elements extend, transversely, to connect the plates, the pillar-like elements being distributed in circular rings or rows concentric with the plates so as to be distributed uniformly in the space, those pillar-like elements which are disposed in inside rows of the braking band having rhombic cross-sections. The rhombic cross-sections of the pillar-like elements which are in inside rows of the band are symmetrical with respect to an axis transverse the direction of flow and each element for connection between the plates extends from one plate to the other whilst remaining within the space.
    • 用于盘式制动盘的具有显着的改进冷却能力的制动带包括两个与轴线同轴的板,彼此面对并间隔开以形成空间,在该空间中轴线向着 带的外侧,板具有相对的表面,柱状元件从该表面横向延伸以连接板,柱状元件分布在与板同心的圆形环或行中,以均匀地分布在 该空间,布置在具有菱形横截面的制动带的内侧行中的那些柱状元件。 在带的内部行中的柱状元件的菱形横截面相对于横向于流动方向的轴对称,并且用于板之间的连接的每个元件从一个板延伸到另一个板,同时保持在 空间。
    • 2. 发明授权
    • Monostabilized dynamic programmable logic array in CMOS technology
    • CMOS技术中的单稳态动态可编程逻辑阵列
    • US5274282A
    • 1993-12-28
    • US970609
    • 1992-10-30
    • Flavio ScarraSiro M. MorgantiGiuseppe Meroni
    • Flavio ScarraSiro M. MorgantiGiuseppe Meroni
    • H03K19/177H03K19/173H03K19/094
    • H03K19/17716
    • The circuit includes an input register (RI); an output register (RU); an AND plane; and an OR plane. The AND plane has vertical lines (Y), which are controlled by the input register, and horizontal lines (L), which include transistors (TA) arranged in series and controlled by respective vertical lines. The horizontal lines are connected to ground by normally-off transistors (TV) and to the power supply by normally-on transistors (TP). These transistors (TV, TP) are controlled by a first clock signal (CK1.about.). The OR plane has horizontal lines (S) and vertical lines (U). The vertical lines (U) of the OR plane contain normally-off transistors (TO) which are controlled by respective horizontal lines of the OR plane. Horizontal lines of the AND plane and horizontal lines of the OR plane are connected by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and ground. In each pair, the normally-on transistor is controlled by a horizontal line of the AND plane, and the normally-off transistor is controlled by a second clock signal (CK2). A horizontal line of the OR plane is connected to the node between the pair. The vertical lines of the OR plane are connected to the power supply by respective transistors (TR), which are controlled by a third clock signal (CK2.about.), and to the output register by pass transistors (P), which are controlled by a fourth clock signal (CK3.about.).
    • 该电路包括一个输入寄存器(RI); 输出寄存器(RU); 一个AND平面; 和OR平面。 AND平面具有由输入寄存器控制的垂直线(Y)和包括串联布置并由相应垂直线控制的晶体管(TA)的水平线(L)。 水平线通过常闭晶体管(TV)连接到地,并通过常开晶体管(TP)连接到电源。 这些晶体管(TV,TP)由第一时钟信号(CK1 DIFFERENCE)控制。 OR平面具有水平线(S)和垂直线(U)。 OR平面的垂直线(U)包含由OR平面的相应水平线控制的常闭晶体管(TO)。 AND平面的水平线和OR平面的水平线通过串联布置在电源和地之间的各对正常导通晶体管(TB)和常关断晶体管(TC)连接。 在每对中,常通晶体管由AND平面的水平线控制,而常闭晶体管由第二时钟信号(CK2)控制。 OR平面的水平线连接到该对之间的节点。 OR平面的垂直线通过由第三时钟信号(CK2 DIFFERENCE)控制的相应晶体管(TR)连接到电源,并且由通过晶体管(P)控制的输出寄存器 第四个时钟信号(CK3 DIFFERENCE)。