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    • 4. 发明授权
    • Analog row black level calibration for CMOS image sensor
    • CMOS图像传感器的模拟行黑电平校准
    • US08405747B2
    • 2013-03-26
    • US13029905
    • 2011-02-17
    • Yaowu MoChen Xu
    • Yaowu MoChen Xu
    • H04N9/64G03F3/08
    • H04N5/361H04N5/3658H04N5/378
    • A CMOS image sensor includes an image pixel array, a dark pixel array, data bit liens, reference bit lines, a driver, comparators, and analog-to-digital converter (“ADC”) circuits. The image pixel array generates analog image signals in response to incident light. The dark pixel array generates analog black reference signals for analog black level calibration of the analog image signals. In one embodiment, the data bit lines each coupled to a different column of image pixels of the image pixel array and the reference bit lines each coupled to a different column of black reference pixels within the dark pixel array. The driver is coupled to the reference bit lines to drive an analog black reference signal. The comparators each couple to one of the data bit lines and each coupled to an output of the driver and offset the analog image signals with the analog black reference signals in an analog domain. The ADC circuits each coupled to an output of a comparator.
    • CMOS图像传感器包括图像像素阵列,暗像素阵列,数据位留置,参考位线,驱动器,比较器和模数转换器(ADC)电路。 图像像素阵列响应于入射光产生模拟图像信号。 暗像素阵列产生用于模拟图像信号的模拟黑电平校准的模拟黑参考信号。 在一个实施例中,每个耦合到图像像素阵列的不同列的图像像素的数据位线和每个耦合到暗像素阵列内的不同列的黑色参考像素的参考位线。 驱动器耦合到参考位线以驱动模拟黑色参考信号。 比较器每个耦合到数据位线中的一个,并且每个耦合到驱动器的输出,并且以模拟域中的模拟黑色参考信号偏移模拟图像信号。 ADC电路各自耦合到比较器的输出端。
    • 5. 发明授权
    • Image sensing pixels with feedback loops for imaging systems
    • 具有用于成像系统的反馈回路的图像感测像素
    • US08390712B2
    • 2013-03-05
    • US12963525
    • 2010-12-08
    • Chen XuYaowu Mo
    • Chen XuYaowu Mo
    • H04N3/14H01L27/00
    • H04N5/3745H01L27/14609
    • An imaging system may include an image sensor array formed from imaging pixels with feedback loops. Each imaging pixel may include an amplifier transistor that is controlled by a voltage on a floating diffusion node and may include a feedback transistor connected between the floating diffusion node and column readout circuitry. The amplifier transistor, together with a current source in the image sensor array, may form a common-source amplifier that inversely amplifies the voltage on the floating diffusion node and provides control signals to the feedback transistor. The common-source amplifier and the feedback transistor may create a feedback loop during image readout operations and during image reset operations that clamps the voltage on the floating diffusion node.
    • 成像系统可以包括由具有反馈回路的成像像素形成的图像传感器阵列。 每个成像像素可以包括由浮动扩散节点上的电压控制的放大器晶体管,并且可以包括连接在浮动扩散节点和列读出电路之间的反馈晶体管。 放大器晶体管与图像传感器阵列中的电流源一起可以形成公共源放大器,其反向放大浮动扩散节点上的电压并向反馈晶体管提供控制信号。 共源放大器和反馈晶体管可以在图像读出操作期间和在将浮动扩散节点上的电压钳位的图像复位操作期间产生反馈回路。
    • 7. 发明申请
    • Clock Tree Planning for an ASIC
    • 时钟树规划ASIC
    • US20120304136A1
    • 2012-11-29
    • US13478272
    • 2012-05-23
    • Liang GeSuoming PuChen XuBo Yu
    • Liang GeSuoming PuChen XuBo Yu
    • G06F17/50
    • G06F17/5068G06F2217/62
    • The present invention discloses a method and system for clock tree planning for an ASIC, the method comprising: determining a netlist and a timing constraint file of the ASIC; creating a sequential device undirected graph for sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file; grouping the sequential devices in the netlist according to the sequential device undirected graph, such that the sequential devices in one group do not have a timing constraint relationship with the sequential devices in another group. The ASIC design method improved by using this method will reduce the design cycle from weeks to days, and enable designer to quickly plan the clock tree, thus reducing the design time and improving the design efficiency.
    • 本发明公开了一种用于ASIC的时钟树规划方法和系统,所述方法包括:确定所述ASIC的网表和定时约束文件; 根据网表中的顺序设备的连接关系和时序约束文件中的顺序设备的时序约束关系,为网表中的顺序设备创建顺序设备无向图; 根据顺序设备无向图对网表中的顺序设备进行分组,使得一组中的顺序设备不具有与另一组中的顺序设备的时序约束关系。 通过使用这种方法改进的ASIC设计方法可以将设计周期从几周缩短到几天,使设计人员能够快速规划时钟树,从而缩短设计时间,提高设计效率。
    • 9. 发明申请
    • ANALOG ROW BLACK LEVEL CALIBRATION FOR CMOS IMAGE SENSOR
    • CMOS图像传感器的模拟黑色水平校准
    • US20120212657A1
    • 2012-08-23
    • US13029905
    • 2011-02-17
    • Yaowu MoChen Xu
    • Yaowu MoChen Xu
    • H04N5/335
    • H04N5/361H04N5/3658H04N5/378
    • A CMOS image sensor includes an image pixel array, a dark pixel array, data bit liens, reference bit lines, a driver, comparators, and analog-to-digital converter (“ADC”) circuits. The image pixel array generates analog image signals in response to incident light. The dark pixel array generates analog black reference signals for analog black level calibration of the analog image signals. In one embodiment, the data bit lines each coupled to a different column of image pixels of the image pixel array and the reference bit lines each coupled to a different column of black reference pixels within the dark pixel array. The driver is coupled to the reference bit lines to drive an analog black reference signal. The comparators each couple to one of the data bit lines and each coupled to an output of the driver and offset the analog image signals with the analog black reference signals in an analog domain. The ADC circuits each coupled to an output of a comparator.
    • CMOS图像传感器包括图像像素阵列,暗像素阵列,数据位留置,参考位线,驱动器,比较器和模数转换器(“ADC”)电路。 图像像素阵列响应于入射光产生模拟图像信号。 暗像素阵列产生用于模拟图像信号的模拟黑电平校准的模拟黑参考信号。 在一个实施例中,每个耦合到图像像素阵列的不同列的图像像素的数据位线和每个耦合到暗像素阵列内的不同列的黑色参考像素的参考位线。 驱动器耦合到参考位线以驱动模拟黑色参考信号。 比较器每个耦合到数据位线中的一个,并且每个耦合到驱动器的输出,并且以模拟域中的模拟黑色参考信号偏移模拟图像信号。 ADC电路各自耦合到比较器的输出端。