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    • 3. 发明授权
      US6064098A Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry 失效
    • Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry
    • 半导体处理方法形成互补金属氧化物半导体存储器等电路，以及存储器等电路
    • US6064098A
    • 2000-05-16
    • US60510
    • 1998-04-14
    • Jeffrey W. Honeycutt , Fernando Gonzalez
    • Jeffrey W. Honeycutt , Fernando Gonzalez
    • H01L21/8238 , H01L21/8239 , H01L27/04 , H01L29/70
    • H01L21/823892 , H01L27/1052
    • A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second a-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron collector layer implant extending to the second n-well periphery to be in electrical connection therewith; the resultant n-type electron collector layer implant being spaced from the first n-well periphery for preventing electrical connection with the first n-well. Memory devices and other circuitry are also disclosed.
    • 形成互补金属氧化物半导体存储器电路的半导体处理方法包括：a）在体半导体衬底上限定存储器阵列区域和外围区域，所述外围区域包括用于形成NMOS外围电路的p阱区域，所述外围区域 包括用于形成相应PMOS外围电路的第一n阱区和第二n阱区，所述第一和第二n阱区彼此分离并具有相应的周边; b）相对于外围第一和第二n阱在衬底上提供图案化掩模层，掩蔽层包括覆盖第一n阱的第一掩蔽块和覆盖第二a阱的第二掩蔽块，第一掩蔽 块掩蔽所述第一n阱周边的侧边缘; 和c）使第一和第二掩模块在适当位置，通过离子注入到本体衬底中提供掩埋的n型电子收集器层; 延伸到第二n阱周边的所得n型电子收集层植入物与其电连接; 所得的n型电子收集器层植入物与第一n阱周边间隔开，以防止与第一n阱的电连接。 还公开了存储器件和其它电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US6040208A Angled ion implantation for selective doping 失效
    • Angled ion implantation for selective doping
    • 用于选择性掺杂的角度离子注入
    • US6040208A
    • 2000-03-21
    • US920535
    • 1997-08-29
    • Jeffrey W. Honeycutt , Fernando Gonzalez , Fawad Ahmed
    • Jeffrey W. Honeycutt , Fernando Gonzalez , Fawad Ahmed
    • H01L21/265 , H01L21/8238
    • H01L21/823807 , H01L21/26586
    • A method of implanting dopants within an exposed first active region on a semiconductor substrate of a semiconductor wafer without doping an exposed second active region of the semiconductor substrate. A barrier wall is formed adjacent to the second active region and projects from the semiconductor substrate to a height above the second active region. A minimal angle relative to an axis perpendicular to the semiconductor substrate is determined at which doping ions directed at the semiconductor substrate must travel so that the barrier wall blocks the doping ions from contacting the second active region. The doping ions are used to bombard the semiconductor substrate at an angle at least as large as the minimal angle previously determined. As a result, the doping ions contact the first active region but do not substantially contact the second active region. The width of the second active region can be formed as greater than that of the first active. In one embodiment, a buried channel of a MOS device is created, the doping concentration of which is profiled so as to optimize both the threshold voltage thereof and the depth to the beginning of the buried channel (.gamma..sub.J).
    • 在半导体晶片的半导体衬底上的暴露的第一有源区内注入掺杂剂的方法，而不掺杂半导体衬底的暴露的第二有源区。 形成与第二有源区相邻的阻挡壁，并且从半导体衬底突出到高于第二有源区的高度。 确定相对于垂直于半导体衬底的轴的最小角度，其中指向半导体衬底的掺杂离子必须行进，使得阻挡壁阻止掺杂离子接触第二有源区。 掺杂离子用于以至少与先前确定的最小角度相同的角度轰击半导体衬底。 结果，掺杂离子接触第一有源区，但基本上不接触第二有源区。 第二有源区的宽度可以形成为大于第一有源区的宽度。 在一个实施例中，产生MOS器件的掩埋沟道，其掺杂浓度被形成为优化其阈值电压和开始埋入沟道（gamma J）的深度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5950079A Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry 失效
    • Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry
    • 形成互补金属氧化物半导体存储器等电路的半导体加工方法
    • US5950079A
    • 1999-09-07
    • US871653
    • 1997-06-09
    • Jeffrey W. Honeycutt , Fernando Gonzalez
    • Jeffrey W. Honeycutt , Fernando Gonzalez
    • H01L21/8238 , H01L21/8239
    • H01L21/823892 , H01L27/1052
    • A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron collector layer implant extending to the second n-well periphery to be in electrical connection therewith; the resultant n-type electron collector layer implant being spaced from the first n-well periphery for preventing electrical connection with the first n-well. Memory devices and other circuitry are also disclosed.
    • 形成互补金属氧化物半导体存储器电路的半导体处理方法包括：a）在体半导体衬底上限定存储器阵列区域和外围区域，所述外围区域包括用于形成NMOS外围电路的p阱区域，所述外围区域 包括用于形成相应PMOS外围电路的第一n阱区和第二n阱区，所述第一和第二n阱区彼此分离并具有相应的周边; b）相对于外围第一和第二n阱在衬底上提供图案化掩模层，掩蔽层包括覆盖第一n阱的第一掩蔽块和覆盖第二n阱的第二掩蔽块，第一掩蔽 块掩蔽所述第一n阱周边的侧边缘; 和c）使第一和第二掩模块在适当位置，通过离子注入到本体衬底中提供掩埋的n型电子收集器层; 延伸到第二n阱周边的所得n型电子收集层植入物与其电连接; 所得的n型电子收集器层植入物与第一n阱周边间隔开，以防止与第一n阱的电连接。 还公开了存储器件和其它电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US5753956A Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry 失效
    • Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry
    • 半导体处理方法形成互补金属氧化物半导体存储器等电路，以及存储器等电路
    • US5753956A
    • 1998-05-19
    • US674655
    • 1996-06-25
    • Jeffrey W. Honeycutt , Fernando Gonzalez
    • Jeffrey W. Honeycutt , Fernando Gonzalez
    • H01L21/8238 , H01L21/8239 , H01L27/04 , H01L29/70
    • H01L21/823892 , H01L27/1052
    • A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron collector layer implant extending to the second n-well periphery to be in electrical connection therewith; the resultant n-type electron collector layer implant being spaced from the first n-well periphery for preventing electrical connection with the first n-well. Memory devices and other circuitry are also disclosed.
    • 形成互补金属氧化物半导体存储器电路的半导体处理方法包括：a）在体半导体衬底上限定存储器阵列区域和外围区域，所述外围区域包括用于形成NMOS外围电路的p阱区域，所述外围区域 包括用于形成相应PMOS外围电路的第一n阱区和第二n阱区，所述第一和第二n阱区彼此分离并具有相应的周边; b）相对于外围第一和第二n阱在衬底上提供图案化掩模层，掩蔽层包括覆盖第一n阱的第一掩蔽块和覆盖第二n阱的第二掩蔽块，第一掩蔽 块掩蔽所述第一n阱周边的侧边缘; 和c）使第一和第二掩模块在适当位置，通过离子注入到本体衬底中提供掩埋的n型电子收集器层; 延伸到第二n阱周边的所得n型电子收集层植入物与其电连接; 所得的n型电子收集器层植入物与第一n阱周边间隔开，以防止与第一n阱的电连接。 还公开了存储器件和其它电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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