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1. 发明授权

US09117677B2 Semiconductor integrated circuit having a resistor and method of forming the same 有权
标题翻译：具有电阻器的半导体集成电路及其形成方法
公开(公告)号：US09117677B2
公开(公告)日：2015-08-25
申请号：US13272389
申请日：2011-10-13
申请人： Wei Yu Ma , Kuo-Ji Chen , Fang-Tsun Chu , Ta-Pen Guo
发明人： Wei Yu Ma , Kuo-Ji Chen , Fang-Tsun Chu , Ta-Pen Guo
IPC分类号： H01L27/06 , H01L21/768 , H01L27/02 , H01L23/522
CPC分类号： H01L27/0266 , H01L21/76895 , H01L23/5228 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.
摘要翻译：本申请公开了一种半导体集成电路，包括其上形成有电气器件的衬底，形成在衬底上的局部互连层，以及形成在局部互连层上的全局互连层。局部互连层具有第一组导电结构，其布置成在各个电气设备之间，电气设备及其相邻的电气设备之一中，或垂直设备和全局互连层之间电连接。第一组导电结构中的至少一个被配置为具有大于50欧姆的电阻值。全局互连层具有布置成经由第一组导电结构电连接电器件的第二组导电结构。

2. 发明申请

US20120081820A1 ESD POWER CLAMP FOR HIGH-VOLTAGE APPLICATIONS 有权
标题翻译： ESD功率钳位用于高压应用
公开(公告)号：US20120081820A1
公开(公告)日：2012-04-05
申请号：US12897585
申请日：2010-10-04
申请人： Fang-Tsun Chu , Kuo-Ji Chen
发明人： Fang-Tsun Chu , Kuo-Ji Chen
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node. The second power supply voltage is lower than a first power supply voltage on the first power supply node. The ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event. The ESD clamp further includes an LV ESD clamp coupled to the second power supply node, wherein the LV ESD clamp includes LV devices with maximum endurable voltages lower than the first power supply voltage.
摘要翻译： ESD钳位包括第一电源节点; ESD检测电路，耦合到所述第一电源节点并且被配置为检测ESD事件; 以及耦合到所述第一电源节点并被配置为将第二电源电压输出到第二电源节点的偏置电路。第二电源电压低于第一电源节点上的第一电源电压。 ESD检测电路被配置为激活偏置电路以响应于ESD事件改变工作状态。 ESD钳位还包括耦合到第二电源节点的LV ESD钳位，其中LV ESD钳位器包括具有低于第一电源电压的最大耐久电压的LV器件。

3. 发明授权

US08179647B2 ESD power clamp for high-voltage applications 有权
标题翻译： ESD电源钳位用于高压应用
公开(公告)号：US08179647B2
公开(公告)日：2012-05-15
申请号：US12897585
申请日：2010-10-04
申请人： Fang-Tsun Chu , Kuo-Ji Chen
发明人： Fang-Tsun Chu , Kuo-Ji Chen
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H02H9/046
摘要： An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node. The second power supply voltage is lower than a first power supply voltage on the first power supply node. The ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event. The ESD clamp further includes an LV ESD clamp coupled to the second power supply node, wherein the LV ESD clamp includes LV devices with maximum endurable voltages lower than the first power supply voltage.
摘要翻译： ESD钳位包括第一电源节点; ESD检测电路，耦合到所述第一电源节点并且被配置为检测ESD事件; 以及耦合到所述第一电源节点并被配置为将第二电源电压输出到第二电源节点的偏置电路。第二电源电压低于第一电源节点上的第一电源电压。 ESD检测电路被配置为激活偏置电路以响应于ESD事件改变工作状态。 ESD钳位还包括耦合到第二电源节点的LV ESD钳位，其中LV ESD钳位器包括具有低于第一电源电压的最大耐久电压的LV器件。

4. 发明授权

US09293606B2 Semiconductor device with seal ring with embedded decoupling capacitor 有权
标题翻译：带封装环的半导体器件带有去耦电容
公开(公告)号：US09293606B2
公开(公告)日：2016-03-22
申请号：US13296410
申请日：2011-11-15
申请人： Kuo-Ji Chen , Wei Yu Ma , Ta-Pen Guo , Hsien-Wei Chen , Hao-Yi Tsai
发明人： Kuo-Ji Chen , Wei Yu Ma , Ta-Pen Guo , Hsien-Wei Chen , Hao-Yi Tsai
IPC分类号： H01L29/93 , H01L29/94 , H01L23/522 , H01L23/528 , H01L23/58 , H01L27/06 , H01L27/08 , H01L49/02
CPC分类号： H01L29/93 , H01L23/5223 , H01L23/5286 , H01L23/585 , H01L27/0629 , H01L27/0805 , H01L28/60 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.
摘要翻译：用于半导体器件的密封环设置有嵌入式去耦电容器。密封环外围围绕密封环区域中的集成电路芯片。至少一个嵌入式去耦电容器可以包括MOS电容器，变容二极管，MOM电容器和具有多个电容器板耦合在一起的叉指电容器。相对的电容器板耦合到不同的电位，并且可以有利地耦合到Vdd和Vss。

5. 发明授权

US09124086B2 Failsafe ESD protection 有权
标题翻译：防止ESD保护
公开(公告)号：US09124086B2
公开(公告)日：2015-09-01
申请号：US13557520
申请日：2012-07-25
申请人： Wei Yu Ma , Kuo-Ji Chen
发明人： Wei Yu Ma , Kuo-Ji Chen
IPC分类号： H02H9/04
CPC分类号： H02H9/04 , H02H9/046
摘要： Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.
摘要翻译：提供了一种或多种用于提供故障安全静电放电（ESD）保护的技术和/或系统。在一个实施例中，通过将电压故障安全（VFS）电源电压连接到NWELL电路接口（例如PMOS晶体管）并将PAD连接到VFS或NWELL电路接口中的至少一个来提供ESD保护。为此，要保护免受ESD（例如，可操作地连接到PAD的电路）的电路具有故障安全ESD保护（例如，使得可以使用非快速恢复的NMOS器件来放电ESD电流，其中非快速恢复NMOS 通常消耗更少的半导体不动产，并且与快速恢复NMOS相比，生产的复杂度较低）。以这种方式，有效地提供故障安全ESD保护。

6. 发明申请

US20130001704A1 Resistors Formed Based on Metal-Oxide-Semiconductor Structures 有权
标题翻译：基于金属氧化物半导体结构形成的电阻器
公开(公告)号：US20130001704A1
公开(公告)日：2013-01-03
申请号：US13170751
申请日：2011-06-28
申请人： Wen-Han Wang , Chen-Chih Wu , Sheng-Fang Cheng , Kuo-Ji Chen
发明人： Wen-Han Wang , Chen-Chih Wu , Sheng-Fang Cheng , Kuo-Ji Chen
IPC分类号： H01L27/06
CPC分类号： H01L28/20 , H01L27/0629
摘要： A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.
摘要翻译：一种器件包括金属氧化物半导体（MOS）器件，其包括栅电极和与栅电极相邻的源/漏区。第一和第二接触插塞形成在相同的MOS部件的两部分上方并电连接，其中相同的MOS部件是栅极电极和源极/漏极区域之一。相同的MOS部件被配置为用作连接在第一和第二接触插塞之间的电阻器。

7. 发明申请

US20110194218A1 ESD Clamp for High Voltage Operation 有权
标题翻译： ESD钳位用于高电压工作
公开(公告)号：US20110194218A1
公开(公告)日：2011-08-11
申请号：US12701996
申请日：2010-02-08
申请人： Kuo-Ji Chen , Guang-Cheng Wang
发明人： Kuo-Ji Chen , Guang-Cheng Wang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) clamp includes a first power source configured to provide a first power supply voltage, a power supply node coupled to the first power source and receiving the power supply voltage; and a first NMOS transistor and a second NMOS transistor coupled in series and between the power supply node and a VSS node. The first NMOS transistor and the second NMOS transistor are low nominal VDD devices with maximum endurable voltages lower than the power supply voltage. The ESD claim further includes an ESD detection circuit including a capacitor coupled between the power supply node and a gate of the second NMOS transistor, and a resistor coupled between the gate of the second NMOS transistor and the VSS node.
摘要翻译：静电放电（ESD）钳位包括被配置为提供第一电源电压的第一电源，耦合到第一电源并接收电源电压的电源节点; 以及串联耦合在电源节点和VSS节点之间的第一NMOS晶体管和第二NMOS晶体管。第一NMOS晶体管和第二NMOS晶体管是具有低于电源电压的最大耐用电压的低标称VDD器件。 ESD声明还包括ESD检测电路，其包括耦合在电源节点和第二NMOS晶体管的栅极之间的电容器，以及耦合在第二NMOS晶体管的栅极和VSS节点之间的电阻器。

8. 发明授权

US07193441B2 Single gate oxide I/O buffer with improved under-drive feature 有权
标题翻译：具有改进的欠驱动特性的单栅极氧化I / O缓冲器
公开(公告)号：US07193441B2
公开(公告)日：2007-03-20
申请号：US10993054
申请日：2004-11-18
申请人： Kuo-Ji Chen , Ker-Min Chen
发明人： Kuo-Ji Chen , Ker-Min Chen
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03K19/00315 , H03K19/00384
摘要： A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first supply voltage and an output node, outputs the first supply voltage to the output node, in response to an input signal. A voltage detection circuit provides the pull-up module with at least one bias voltage selected from a predetermined set of voltage levels, wherein the voltage detection circuit selects the bias voltage upon detecting a reduction of the first supply voltage.
摘要翻译：耦合在高电压电路和低电压电路之间的输入/输出缓冲电路中使用的高压缓冲器模块在第一电源电压和其互补的第二电源电压之间工作。耦合在第一电源电压和输出节点之间的上拉模块响应于输入信号将第一电源电压输出到输出节点。电压检测电路为上拉模块提供从预定的一组电压电平选择的至少一个偏置电压，其中电压检测电路在检测到第一电源电压的降低时选择偏置电压。

9. 发明授权

US07151391B2 Integrated circuit for level-shifting voltage levels 有权
标题翻译：用于电平转换电压电平的集成电路
公开(公告)号：US07151391B2
公开(公告)日：2006-12-19
申请号：US10852390
申请日：2004-05-24
申请人： Ker-Min Chen , Kuo-Ji Chen
发明人： Ker-Min Chen , Kuo-Ji Chen
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K17/102
摘要： An integrated circuit for level-shifting voltage signals comprising an input/output pad, and an input/output circuit coupled to the output pad having a plurality of devices operating with a bias supply voltage operable to shift between the range of the bias supply voltage to the range of an input/output supply voltage that is higher than the bias supply voltage is provided. In addition, an integrated circuit comprises an input circuit coupled to an input pad operable to input shift signals from an input/output supply voltage range to a core supply voltage range, an output circuit coupled to an output pad operable to shift output signals from a bias supply voltage range to an input/output supply voltage range, and a core circuit coupled to the input and output circuits and having a gate dielectric thickness substantially similar to a gate dielectric thickness of the input circuit and the output circuit.
摘要翻译：一种用于电平移动电压信号的集成电路，包括输入/输出焊盘以及耦合到输出焊盘的输入/输出电路，该输出/输出电路具有多个器件，工作在偏置电源电压下工作，该偏置电源电压可操作以在偏置电源电压的范围提供高于偏置电源电压的输入/输出电源电压的范围。此外，集成电路包括耦合到输入焊盘的输入电路，其可操作以将输入/输出电源电压范围的移位信号输入到核心电源电压范围;耦合到输出焊盘的输出电路，其可操作以将输出信号从偏置电源电压范围到输入/输出电源电压范围，以及耦合到输入和输出电路的核心电路，并且具有基本上类似于输入电路和输出电路的栅介质厚度的栅介质厚度。

10. 发明申请

US20060186921A1 Dual-voltage three-state buffer circuit with simplified tri-state level shifter 有权
标题翻译：具有简化三态电平转换器的双电压三态缓冲电路
公开(公告)号：US20060186921A1
公开(公告)日：2006-08-24
申请号：US11063961
申请日：2005-02-23
申请人： Kuo-Ji Chen , Ker-Min Chen
发明人： Kuo-Ji Chen , Ker-Min Chen
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , H03K19/0013 , H03K19/09429
摘要： A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.
摘要翻译：双电压三态缓冲器电路控制后驱动电路以三态模式工作，并且包括在低电源电压下工作的三态逻辑控制模块，用于从三端接收一个或多个输入的电平转换器状态逻辑控制模块，并且用于控制电平移位器的两个差分输出的输出控制电路和由电平移位器的两个差分输出驱动的后驱动电路，其中电平移位器，输出控制电路，后驱动器电路在高电源电压下工作，并且其中当三态逻辑控制模块产生用于将后驱动电路置于高阻态的输入时，输出控制电路与电平移位器一起工作以关断PMOS 和后驱动电路的NMOS晶体管，同时将电平移位器与高电源电压隔离。

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