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1. 发明授权

US07082517B2 Superscalar microprocessor having multi-pipe dispatch and execution unit 失效
标题翻译：超标量微处理器具有多管调度和执行单元
公开(公告)号：US07082517B2
公开(公告)日：2006-07-25
申请号：US10435806
申请日：2003-05-12
申请人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
发明人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/3017 , G06F9/3836 , G06F9/3885
摘要： In a computer system for use as a symetrical multiprocessor, a superscalar microprocessor apparatus allows dispatching and executing multi-cycle and complex instructions Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). Multiple execution pipes correspond to the instruction dispatch ports and the execution unit is a Fixed Point Unit (FXU) which contains three execution dataflow pipes (X, Y and Z) and one control pipe (R). The FXU logic then execute these instructions on the available FXU pipes. This results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.
摘要翻译：在用作对称多处理器的计算机系统中，超标量微处理器装置允许调度和执行多周期和复杂指令。在调度单元中生成一些控制信号，并且通过指令发送到定点单元（FXU）。多个执行管道对应于指令调度端口，执行单元是包含三个执行数据流管道（X，Y和Z）和一个控制管道（R）的定点单元（FXU）。然后，FXU逻辑在可用的FXU管道上执行这些说明。这导致最佳性能，很少或没有其他并发症。所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。

2. 发明授权

US07010676B2 Last iteration loop branch prediction upon counter threshold and resolution upon counter one 失效
标题翻译：最后迭代循环分支预测在计数器阈值和分辨率之间
公开(公告)号：US07010676B2
公开(公告)日：2006-03-07
申请号：US10436296
申请日：2003-05-12
申请人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
发明人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
IPC分类号： G06F9/38
CPC分类号： G06F9/325 , G06F9/3844
摘要： An embodiment of the invention is a processor for processing loop branch instructions. The processor includes an instruction unit for fetching and decoding instructions including at least one loop branch instruction. A branch prediction unit predicts target instructions to be fetched and decoded by the instruction unit in response to the loop branch instruction. An execution unit executes instructions from the instruction unit and maintains a counter indicating an iteration of a loop. The execution unit includes detection logic for detecting when the counter equals a threshold and notifies the branch prediction unit when the counter equals the threshold.
摘要翻译：本发明的实施例是用于处理回路分支指令的处理器。所述处理器包括用于对包括至少一个环路分支指令的指令进行读取和解码的指令单元。分支预测单元响应于循环分支指令预测由指令单元获取和解码的目标指令。执行单元从指令单元执行指令，并且维护指示循环迭代的计数器。执行单元包括用于检测计数器何时等于阈值的检测逻辑，并且当计数器等于阈值时通知分支预测单元。

3. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

4. 发明授权

US07085917B2 Multi-pipe dispatch and execution of complex instructions in a superscalar processor 有权
标题翻译：超标量处理器中的多管调度和复杂指令的执行
公开(公告)号：US07085917B2
公开(公告)日：2006-08-01
申请号：US10435983
申请日：2003-05-12
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr. , Timothy J. Slegel
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr. , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/325 , G06F9/3017 , G06F9/3836 , G06F9/3885
摘要： In a computer system, a method and apparatus for dispatching and executing multi-cycle and complex instructions. The method results in maximum performance for such without impacting other areas in the processor such as decode, grouping or dispatch units. This invention allows multi-cycle and complex instructions to be dispatched to one port but executed in multiple execution pipes without cracking the instruction and without limiting it to a single execution pipe. Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). The FXU logic then execute these instructions on the available FXU pipes. This method results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.
摘要翻译：在计算机系统中，用于调度和执行多周期和复杂指令的方法和装置。该方法导致最大的性能，而不会影响处理器中的其他区域，如解码，分组或调度单元。本发明允许将多周期和复杂指令分派到一个端口，但是在多个执行管道中执行，而不会破坏指令，而不限于单个执行管道。在调度单元中生成一些控制信号，并通过指令发送到定点单元（FXU）。然后，FXU逻辑在可用的FXU管道上执行这些说明。这种方法导致最佳性能，很少或没有其他并发症。所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。

5. 发明授权

US07921279B2 Operand and result forwarding between differently sized operands in a superscalar processor 失效
标题翻译：操作数和结果在超标量处理器中的不同大小的操作数之间转发
公开(公告)号：US07921279B2
公开(公告)日：2011-04-05
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

6. 发明授权

US09280398B2 Major branch instructions 有权
公开(公告)号：US09280398B2
公开(公告)日：2016-03-08
申请号：US13362574
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F9/46 , G06F9/52 , G06F9/38 , G06F9/32
CPC分类号： G06F9/528 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

7. 发明授权

US08904246B2 Variable acknowledge rate to reduce bus contention in presence of communication errors 有权
标题翻译：在存在通信错误的情况下减少总线争用的可变确认速率
公开(公告)号：US08904246B2
公开(公告)日：2014-12-02
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/00
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

8. 发明授权

US08904100B2 Process identifier-based cache data transfer 有权
标题翻译：基于进程标识符的缓存数据传输
公开(公告)号：US08904100B2
公开(公告)日：2014-12-02
申请号：US13493636
申请日：2012-06-11
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/02
CPC分类号： G06F17/30982 , G06F12/0817 , G06F12/12
摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.
摘要翻译：本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

9. 发明申请

US20130290802A1 VARIABLE ACKNOWLEDGE RATE TO REDUCE BUS CONTENTION IN PRESENCE OF COMMUNICATION ERRORS 有权
标题翻译：在通信错误存在的情况下，可降低总线容量的可变确认值
公开(公告)号：US20130290802A1
公开(公告)日：2013-10-31
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

10. 发明授权

US08930950B2 Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors 有权
标题翻译：在计算环境中迁移线程的管理，以将多个线程模式处理器转换为单线程模式处理器
公开(公告)号：US08930950B2
公开(公告)日：2015-01-06
申请号：US13353550
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4856 , G06F9/505 , G06F9/5088
摘要： Threads of a computing environment are managed to improve system performance. Threads are migrated between processors to take advantage of single thread processing mode, when possible. As an example, inactive threads are migrated from one or more processors, potentially freeing-up one or more processors to execute an active thread. Active threads are migrated from one processor to another to transform multiple threading mode processors to single thread mode processors.
摘要翻译：管理计算环境的线程以提高系统性能。线程在处理器之间迁移，以尽可能利用单线程处理模式。作为示例，非活动线程从一个或多个处理器迁移，潜在地释放一个或多个处理器以执行活动线程。活动线程从一个处理器迁移到另一个处理器，以将多个线程模式处理器转换为单线程模式处理器。

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