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1. 发明授权

US08643403B2 Sampling 有权
标题翻译：采样
公开(公告)号：US08643403B2
公开(公告)日：2014-02-04
申请号：US13712494
申请日：2012-12-12
申请人： Fujitsu Semiconductor Limited
发明人： Ian Juso Dedic , Gavin Lambertus Allen
IPC分类号： G11C27/02
CPC分类号： H03M1/0614 , G11C27/02 , H01H9/54 , H03K17/00 , H03L7/00 , H03L7/091 , H03M1/002 , H03M1/0881 , H03M1/1009 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/126 , Y10T307/76
摘要： There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.
摘要翻译：公开了被配置为由基本正弦时钟信号驱动的电流模式时间交织采样电路。这种电路可以并入ADC电路中，例如作为IC芯片上的集成电路。所公开的电路能够自行校准而不脱机。

2. 发明申请

US20130127648A1 SAMPLING 有权
公开(公告)号：US20130127648A1
公开(公告)日：2013-05-23
申请号：US13712798
申请日：2012-12-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso DEDIC , Gavin Lambertus Allen
IPC分类号： H03K17/00 , H03M1/10
CPC分类号： H03M1/0614 , G11C27/02 , H01H9/54 , H03K17/00 , H03L7/00 , H03L7/091 , H03M1/002 , H03M1/0881 , H03M1/1009 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/126 , Y10T307/76
摘要： There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

3. 发明授权

US09054722B2 Circuitry and methods for use in mixed-signal circuitry 有权
标题翻译：用于混合信号电路的电路和方法
公开(公告)号：US09054722B2
公开(公告)日：2015-06-09
申请号：US14025330
申请日：2013-09-12
申请人： Fujitsu Semiconductor Limited
发明人： Ian Juso Dedic , Saul Darzy , Gavin Lambertus Allen
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/10 , H03M1/745
摘要： A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.
摘要翻译：一种校准开关电路的方法，所述开关电路包括连接到所述测量节点的测量节点和多个输出开关，并且所述电路在一系列时钟周期的每个时钟周期中被配置以控制是否一个或者更多的所述输出开关基于输入数据携带给定的电流，该方法包括：向电路输入多个不同的数据序列，每个序列导致给定的电压模式由于电流通过而在测量节点处出现输出开关; 测量每个所述序列在测量节点处出现的电压; 并根据所述测量的结果校准开关电路。

4. 发明申请

US20150070074A1 CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY 有权
标题翻译：用于混合信号电路的电路和方法
公开(公告)号：US20150070074A1
公开(公告)日：2015-03-12
申请号：US14473706
申请日：2014-08-29
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso DEDIC , Saul Darzy , Gavin Lambertus Allen
IPC分类号： H03K17/16
CPC分类号： H03K17/145 , H03K17/162 , H03K17/302 , H03M1/0617 , H03M1/662 , H03M1/687 , H03M1/745 , H03M1/747
摘要： Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.
摘要翻译：用于数模转换器的开关电路，所述电路包括：公共节点; 第一和第二输出节点; 以及多个开关，其连接在所述公共节点与所述第一和第二输出节点之间，并且可在基于输入数据的一系列时钟周期的每个时钟周期中工作，以将所述公共节点导电地连接到所述第一或第二输出节点多个路径中的给定一个路径，其中所述电路被布置为使得沿着从所述公共节点到所述第一或第二输出节点的每个所述路径串行地提供数据控制的开关和时钟控制的开关。

5. 发明授权

US08547160B2 Sampling 有权
公开(公告)号：US08547160B2
公开(公告)日：2013-10-01
申请号：US13712522
申请日：2012-12-12
申请人： Fujitsu Semiconductor Limited
发明人： Ian Juso Dedic , Gavin Lambertus Allen
IPC分类号： H03K17/00
CPC分类号： H03M1/0614 , G11C27/02 , H01H9/54 , H03K17/00 , H03L7/00 , H03L7/091 , H03M1/002 , H03M1/0881 , H03M1/1009 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/126 , Y10T307/76
摘要： There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

6. 发明授权

US09178523B2 Circuitry and methods for use in mixed-signals circuitry 有权
标题翻译：用于混合信号电路的电路和方法
公开(公告)号：US09178523B2
公开(公告)日：2015-11-03
申请号：US14473789
申请日：2014-08-29
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso Dedic , Gavin Lambertus Allen , Saul Darzy
IPC分类号： H03M1/66 , H03M1/06 , H03K3/012 , H03M1/12 , H03K17/06 , H03K17/16 , H03K17/693
CPC分类号： H03M1/0624 , H03K3/012 , H03K17/063 , H03K17/162 , H03K17/693 , H03M1/12 , H03M1/66
摘要： A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.
摘要翻译：一种开关电路，包括：具有控制端的主开关; 以及连接到主开关的控制端子的时钟通路部分，以向其施加驱动时钟信号以驱动主开关，其中该电路被配置为可控制地将施加偏压电压施加到时钟通路部分，以便将施加到主开关的控制端的驱动时钟信号的电压电平偏置。

7. 发明申请

US20150077278A1 SAMPLING 有权
标题翻译：采样
公开(公告)号：US20150077278A1
公开(公告)日：2015-03-19
申请号：US14553598
申请日：2014-11-25
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso Dedic , Gavin Lambertus Allen
IPC分类号： H03M1/06 , H03M1/12 , H03M1/08 , H03M1/00
CPC分类号： H03M1/0614 , G11C27/02 , H01H9/54 , H03K17/00 , H03L7/00 , H03L7/091 , H03M1/002 , H03M1/0881 , H03M1/1009 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/126 , Y10T307/76
摘要： There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.
摘要翻译：公开了被配置为由基本正弦时钟信号驱动的电流模式时间交织采样电路。这种电路可以并入ADC电路中，例如作为IC芯片上的集成电路。所公开的电路能够自行校准而不脱机。

8. 发明申请

US20150070201A1 CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY 有权
标题翻译：用于混合信号电路的电路和方法
公开(公告)号：US20150070201A1
公开(公告)日：2015-03-12
申请号：US14025303
申请日：2013-09-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso DEDIC , Saul Darzy , Gavin Lambertus Allen
IPC分类号： H03M1/66 , H03M1/12
CPC分类号： H03M1/0624 , H03M1/12 , H03M1/747
摘要： Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analogue-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analogue converter, wherein: the first switching-circuitry unit is configured to sample an input analogue signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analogue signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of clock signals have the same specifications as one another.
摘要翻译：混合信号电路，包括：用于模拟 - 数字转换器的第一开关电路单元; 以及用于数模转换器的第二开关电路单元，其中：所述第一开关电路单元被配置为基于第一多个时钟信号对输入的模拟信号进行采样并输出多个采样; 第二切换电路单元被配置为基于多个数据信号和第二多个时钟信号产生输出模拟信号; 并且第一和第二多个时钟信号具有彼此相同的规格。

9. 发明授权

US08976050B1 Circuitry and methods for use in mixed-signal circuitry 有权
标题翻译：用于混合信号电路的电路和方法
公开(公告)号：US08976050B1
公开(公告)日：2015-03-10
申请号：US14025303
申请日：2013-09-12
申请人： Fujitsu Semiconductor Limited
发明人： Ian Juso Dedic , Saul Darzy , Gavin Lambertus Allen
IPC分类号： H03M1/12 , H03M1/66
CPC分类号： H03M1/0624 , H03M1/12 , H03M1/747
摘要： Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analog-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analog converter, wherein: the first switching-circuitry unit is configured to sample an input analog signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analog signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of dock signals have the same specifications as one another.
摘要翻译：混合信号电路，包括：用于模数转换器的第一开关电路单元; 以及用于数模转换器的第二开关电路单元，其中：所述第一开关电路单元被配置为对输入的模拟信号进行采样，并且基于第一多个时钟信号输出多个采样; 第二开关电路单元被配置为基于多个数据信号和第二多个时钟信号产生输出模拟信号; 并且第一和第二多个码头信号具有彼此相同的规格。

10. 发明申请

US20130147647A1 SAMPLING 有权
公开(公告)号：US20130147647A1
公开(公告)日：2013-06-13
申请号：US13712522
申请日：2012-12-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso DEDIC , Gavin Lambertus Allen
IPC分类号： H03L7/00 , H03M1/12
CPC分类号： H03M1/0614 , G11C27/02 , H01H9/54 , H03K17/00 , H03L7/00 , H03L7/091 , H03M1/002 , H03M1/0881 , H03M1/1009 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/126 , Y10T307/76
摘要： There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

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