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1. 发明申请

US20140320171A1 ELECTRONIC CIRCUIT 有权
标题翻译：电子电路
公开(公告)号：US20140320171A1
公开(公告)日：2014-10-30
申请号：US14191135
申请日：2014-02-26
申请人： FUJITSU LIMITED
发明人： Takayuki HAMADA , Sanroku TSUKAMOTO
IPC分类号： G01R19/00
CPC分类号： G01R19/0038 , G01R19/0092
摘要： An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.
摘要翻译：电子电路包括：加权电路，被配置为通过根据可修改系数加权和组合第一输入信号和第二输入信号来产生第一电流，并且通过加权并组合第一反相信号和第二反相信号来产生第二电流所述第一反相信号是所述第一输入信号的反相信号，所述第二反相信号是所述第二输入信号的反相信号; 以及判定电路，被配置为通过将所述第一电流与所述第二电流进行比较来决定输出信号。

2. 发明申请

US20140320192A1 INTERPOLATION CIRCUIT AND RECEIVING CIRCUIT 有权
标题翻译：插值电路和接收电路
公开(公告)号：US20140320192A1
公开(公告)日：2014-10-30
申请号：US14179133
申请日：2014-02-12
申请人： FUJITSU LIMITED
发明人： Takayuki HAMADA , Sanroku TSUKAMOTO
IPC分类号： G06G7/30
CPC分类号： G06G7/30
摘要： An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.
摘要翻译：插值电路包括：多个保持电路，其被配置为按时间顺序保持对应的输入数据输入; 以及生成电路，被配置为通过基于内插代码赋予输入与多个保持电路按时间顺序相邻并由多个保持电路保持的数据并将加权数据组合在一起的输入数据来生成内插数据。

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