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1. 发明申请

US20190286077A1 OPTIMIZATION APPARATUS AND CONTROL METHOD FOR OPTIMIZATION APPARATUS 审中-公开
公开(公告)号：US20190286077A1
公开(公告)日：2019-09-19
申请号：US16284101
申请日：2019-02-25
申请人： FUJITSU LIMITED
发明人： Jumpei KOYAMA , Kazuya TAKEMOTO , Motomu TAKATSU , Satoshi MATSUBARA , Takayuki SHIBASAKI , Noboru YONEOKA , Toshiyuki MIYAZAWA , Akihiko OHWADA , Sanroku TSUKAMOTO
IPC分类号： G05B13/04 , G06N3/08 , G06N3/04 , G06F17/11
摘要： A problem is inputted into an operation unit. A computation unit searches for a ground state of an Ising model. A management unit converts the problem inputted from the operation unit to the Ising model, inputs the Ising model produced by conversion and initial operating conditions into the computation unit, and has the computation unit search for the ground state using overall operating conditions produced by changing the initial operating conditions based on a result of the computation unit searching for the ground state using the initial operating conditions.

2. 发明申请

US20190244098A1 OPTIMIZATION SYSTEM, OPTIMIZATION APPARATUS, AND OPTIMIZATION SYSTEM CONTROL METHOD 审中-公开
公开(公告)号：US20190244098A1
公开(公告)日：2019-08-08
申请号：US16266165
申请日：2019-02-04
申请人： FUJITSU LIMITED
发明人： Sanroku TSUKAMOTO , SATOSHI MATSUBARA , Hirotaka TAMURA
IPC分类号： G06N3/08 , G06N3/04
CPC分类号： G06N3/08 , G06N3/0472
摘要： An optimization apparatus calculates a first portion, among energy change caused by change in value of a neuron of a neuron group, caused by influence of another neuron of the neuron group, determines whether to allow updating the value, based on a sum of the first and second portions of the energy change, and repeats a process of updating or maintaining the value according to the determination. An arithmetic processing apparatus calculates the second portion caused by influence of a neuron not belonging to the neuron group and an initial value of the sum. A control apparatus transmits data for calculating the second portion and the initial value to the arithmetic processing apparatus, and the initial value and data for calculating the first portion to the optimization apparatus, and receives the initial value from the arithmetic processing apparatus, and a value of the neuron group from the optimization apparatus.

3. 发明申请

US20150103962A1 RECEIVING DEVICE AND DATA INTERPOLATION PROCESSING METHOD 有权
标题翻译：接收设备和数据插值处理方法
公开(公告)号：US20150103962A1
公开(公告)日：2015-04-16
申请号：US14477674
申请日：2014-09-04
申请人： FUJITSU LIMITED
发明人： Sanroku TSUKAMOTO
IPC分类号： H03M1/12
CPC分类号： H03M1/1255 , G11C27/024 , H03M1/0678 , H03M1/0863 , H03M1/12 , H03M1/125
摘要： There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed.
摘要翻译：提供了一种接收装置，包括：多个内插单元电路，每个内插单元电路被配置为基于插值比率对输入数据进行异步采样而获得的采样值的内插处理，使得与输入数据同步的采样数据并且产生时间连续，其中一个内插单元电路与用于执行插值比的切换的通道之前的通道的另一个内插单元电路并联提供。

4. 发明申请

US20140320192A1 INTERPOLATION CIRCUIT AND RECEIVING CIRCUIT 有权
标题翻译：插值电路和接收电路
公开(公告)号：US20140320192A1
公开(公告)日：2014-10-30
申请号：US14179133
申请日：2014-02-12
申请人： FUJITSU LIMITED
发明人： Takayuki HAMADA , Sanroku TSUKAMOTO
IPC分类号： G06G7/30
CPC分类号： G06G7/30
摘要： An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.
摘要翻译：插值电路包括：多个保持电路，其被配置为按时间顺序保持对应的输入数据输入; 以及生成电路，被配置为通过基于内插代码赋予输入与多个保持电路按时间顺序相邻并由多个保持电路保持的数据并将加权数据组合在一起的输入数据来生成内插数据。

5. 发明申请

US20170220924A1 BOLTZMANN MACHINE, METHOD FOR CONTROLLING BOLTZMANN MACHINE, AND INFORMATION PROCESSING DEVICE HAVING BOLTZMANN MACHINE 审中-公开
公开(公告)号：US20170220924A1
公开(公告)日：2017-08-03
申请号：US15419238
申请日：2017-01-30
申请人： FUJITSU LIMITED
发明人： Takumi DANJO , Sanroku TSUKAMOTO , Hirotaka TAMURA
IPC分类号： G06N3/04 , G06N7/00
CPC分类号： G06N3/04 , G06N3/0445 , G06N3/0472 , G06N3/063 , G06N7/005
摘要： Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.

6. 发明申请

US20140320171A1 ELECTRONIC CIRCUIT 有权
标题翻译：电子电路
公开(公告)号：US20140320171A1
公开(公告)日：2014-10-30
申请号：US14191135
申请日：2014-02-26
申请人： FUJITSU LIMITED
发明人： Takayuki HAMADA , Sanroku TSUKAMOTO
IPC分类号： G01R19/00
CPC分类号： G01R19/0038 , G01R19/0092
摘要： An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.
摘要翻译：电子电路包括：加权电路，被配置为通过根据可修改系数加权和组合第一输入信号和第二输入信号来产生第一电流，并且通过加权并组合第一反相信号和第二反相信号来产生第二电流所述第一反相信号是所述第一输入信号的反相信号，所述第二反相信号是所述第二输入信号的反相信号; 以及判定电路，被配置为通过将所述第一电流与所述第二电流进行比较来决定输出信号。

7. 发明申请

US20160173114A1 A/D CONVERTER AND A/D CONVERTER CALIBRATING METHOD 有权
标题翻译： A / D转换器和A / D转换器校准方法
公开(公告)号：US20160173114A1
公开(公告)日：2016-06-16
申请号：US15044632
申请日：2016-02-16
申请人： FUJITSU LIMITED
发明人： Masaya KIBUNE , Sanroku TSUKAMOTO
IPC分类号： H03M1/10 , H03M1/46
CPC分类号： H03M1/1009 , H03M1/1057 , H03M1/462 , H03M1/468
摘要： An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit.
摘要翻译： A / D转换器包括A / D转换单元，直方图生成存储单元和控制单元。 A / D转换单元被配置为接收输入电压，执行模数转换并输出数字数据，并且直方图生成存储单元被配置为接收数字数据，生成用于波形的直方图输入电压，并存储其中生成的直方图。控制单元被配置为基于存储在直方图生成存储单元中的直方图来控制A / D转换单元的模数转换特性。

8. 发明申请

US20130321187A1 ANALOG-TO-DIGITAL CONVERTER AND ELECTRONIC APPARATUS 有权
标题翻译：模拟数字转换器和电子设备
公开(公告)号：US20130321187A1
公开(公告)日：2013-12-05
申请号：US13868711
申请日：2013-04-23
申请人： FUJITSU LIMITED
发明人： Yanfei CHEN , Sanroku TSUKAMOTO
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/0678 , H03M1/468
摘要： An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.
摘要翻译：模数转换器包括具有预定数量的灰度转换级的数模（DA）转换部分，并且被配置为使预定数量的灰度转换级中的每一个将数字信号转换为模拟信号，输出转换后的模拟信号，主比较器被配置为基于从DA转换部分输出的模拟信号与预定参考电平之间的第一比较结果输出二进制信号，以及第二子比较器，其偏移量较小比相对于主比较器的量化单位，并且被配置为基于从DA转换部分输出的模拟信号和预定参考电平之间的第二比较结果来输出二进制信号。

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