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1. 发明申请

US20190280779A1 SIGNAL PROCESSING CIRCUIT AND OPTICAL RECEIVING DEVICE 审中-公开
公开(公告)号：US20190280779A1
公开(公告)日：2019-09-12
申请号：US16255963
申请日：2019-01-24
申请人： FUJITSU LIMITED
发明人： Yuya IMOTO , KAZUHIKO HATAE , Nobukazu KOIZUMI , Yasuo OHTOMO , Masato OOTA , Masashi Sato , Daisuke SASAKI
IPC分类号： H04B10/61 , H04L25/03 , H04B10/69
摘要： A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.

2. 发明申请

US20180123701A1 AMPLITUDE ADJUSTMENT CIRCUIT, DIGITAL COHERENT RECEIVER, AND AMPLITUDE ADJUSTMENT METHOD 审中-公开
公开(公告)号：US20180123701A1
公开(公告)日：2018-05-03
申请号：US15726428
申请日：2017-10-06
申请人： FUJITSU LIMITED
发明人： Masashi Sato , KAZUHIKO HATAE , Nobukazu KOIZUMI , Yasuo OHTOMO , Masato OOTA , Daisuke SASAKI , Yuya IMOTO
IPC分类号： H04B10/61 , H04L1/00 , H04B10/2569 , H04J14/06 , H03K7/02
CPC分类号： H04B10/6165 , H03K7/02 , H04B10/2569 , H04B10/612 , H04B10/614 , H04B10/6151 , H04B10/616 , H04J14/06 , H04L1/0039 , H04L25/03
摘要： An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.

3. 发明申请

US20170012803A1 ADAPTIVE EQUALIZATION CIRCUIT, DIGITAL COHERENT RECEIVER, AND ADAPTIVE EQUALIZATION METHOD 有权
标题翻译：自适应均衡电路，数字相关接收器和自适应均衡方法
公开(公告)号：US20170012803A1
公开(公告)日：2017-01-12
申请号：US15203004
申请日：2016-07-06
申请人： FUJITSU LIMITED
发明人： Daisuke SASAKI , KAZUHIKO HATAE , TOMOKI KATOU , Nobukazu KOIZUMI , Masato OOTA , Yasuo OHTOMO , MANABU YAMAZAKI , Masashi Sato
IPC分类号： H04L25/03 , H04B10/61
CPC分类号： H04L25/03019 , H04B10/6161 , H04B10/6162 , H04B10/6164 , H04L25/0224 , H04L2025/03681
摘要： A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a setting value based on the second signal.
摘要翻译：电路包括：计算电路，被配置为基于通过补偿电路补偿第一信号获得的第二信号，计算重复包含在输入到自适应均衡器中的第一信号中的预定训练序列模式的噪声功率;频道基于第二信号的预测值和预定训练序列模式; 以及平均电路，被配置为在基于预定训练的频率偏移的估计值中，基于具有等于或小于预定功率的噪声功率的预定训练序列模式来获得频率偏移的估计值的平均值序列模式，其中所述补偿电路被配置为基于所述平均值补偿所述预定训练序列模式的频率偏移，从而获得所述第二信号，并且所述自适应均衡器被配置为执行所述第一信号的自适应均衡处理具有基于第二信号的设定值。

4. 发明授权

US10931485B2 Adaptive equalization circuit and optical receiver 有权
公开(公告)号：US10931485B2
公开(公告)日：2021-02-23
申请号：US16733282
申请日：2020-01-03
申请人： FUJITSU LIMITED
发明人： Yuya Imoto , Kazuhiko Hatae , Nobukazu Koizumi , Yasuo Ohtomo , Masashi Sato , Daisuke Sasaki
IPC分类号： H04L25/03 , H04L25/02
摘要： An adaptive equalization circuit includes: a first filter configure to perform filtering on an input signal based on a tap coefficient; an applying circuit configured to apply, to the signal, noise outside a band of the signal; and a controller configured to set, for the first filter, the tap coefficient that compensates for transmission line characteristics of the signal, based on the signal to which the noise is applied by the applying circuit.

5. 发明授权

US10560199B2 Signal processing circuit and optical receiving device 有权
公开(公告)号：US10560199B2
公开(公告)日：2020-02-11
申请号：US16255963
申请日：2019-01-24
申请人： FUJITSU LIMITED
发明人： Yuya Imoto , Kazuhiko Hatae , Nobukazu Koizumi , Yasuo Ohtomo , Masato Oota , Masashi Sato , Daisuke Sasaki
IPC分类号： H04B10/61 , H04L25/03 , H04B10/69 , H04B10/2569 , H04L5/06 , H04L27/26
摘要： A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.

6. 发明申请

US20160134261A1 SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND SIGNAL PROCESSING SYSTEM 有权
标题翻译：信号处理装置，信号处理方法和信号处理系统
公开(公告)号：US20160134261A1
公开(公告)日：2016-05-12
申请号：US14841834
申请日：2015-09-01
申请人： FUJITSU LIMITED
发明人： Masashi Sato , KAZUHIKO HATAE , TOMOKI KATOU , Nobukazu KOIZUMI , Masato OOTA , Yasuo OHTOMO , MANABU YAMAZAKI , Daisuke SASAKI
IPC分类号： H03H17/02
CPC分类号： H04B10/616 , H03H17/0294 , H03H21/0012 , H04B10/612
摘要： A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.
摘要翻译：信号处理装置包括：滤波器; 以及滤波器控制电路，其中所述滤波器控制电路被配置为：检测从所述滤波器输出的信号的功率; 确定权力所属的多个数值范围之一; 根据确定结果更新滤波器的滤波器系数; 计数具有第一值或更多值的信号的数量; 当信号的数量变为第二值时，设置成为多个数值范围中的一个或多个边界的每一个都不被确定的目标的无效区域; 并且基于信号的数量来控制无效区域的宽度。

7. 发明授权

US10177855B2 Amplitude adjustment circuit, digital coherent receiver, and amplitude adjustment method 有权
公开(公告)号：US10177855B2
公开(公告)日：2019-01-08
申请号：US15726428
申请日：2017-10-06
申请人： FUJITSU LIMITED
发明人： Masashi Sato , Kazuhiko Hatae , Nobukazu Koizumi , Yasuo Ohtomo , Masato Oota , Daisuke Sasaki , Yuya Imoto
IPC分类号： H04B10/60 , H04B10/61 , H03K7/02 , H04B10/2569 , H04J14/06 , H04L1/00 , H04L25/03
摘要： An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.

8. 发明授权

US09680667B2 Adaptive equalization circuit, digital coherent receiver, and adaptive equalization method 有权
公开(公告)号：US09680667B2
公开(公告)日：2017-06-13
申请号：US15203004
申请日：2016-07-06
申请人： FUJITSU LIMITED
发明人： Daisuke Sasaki , Kazuhiko Hatae , Tomoki Katou , Nobukazu Koizumi , Masato Oota , Yasuo Ohtomo , Manabu Yamazaki , Masashi Sato
IPC分类号： H04L25/03 , H04B10/61 , H04L25/02
CPC分类号： H04L25/03019 , H04B10/6161 , H04B10/6162 , H04B10/6164 , H04L25/0224 , H04L2025/03681
摘要： A circuit includes a calculation circuit configured to calculate a noise power of a predetermined-training-sequence pattern repeatedly included in a first signal input into an adaptive equalizer, based on a second signal obtained by compensating the first signal by a compensation circuit, a channel-estimation value based on the second signal, and the predetermined-training-sequence pattern; and an average circuit configured to obtain an average value of estimation values of frequency offsets based on the predetermined-training-sequence pattern having the noise power equal to or smaller than a predetermined power, among estimation values of frequency offsets based on the predetermined-training-sequence pattern, wherein the compensation circuit is configured to compensate a frequency offset of the predetermined-training sequence pattern based on the average value and thereby obtain the second signal, and the adaptive equalizer is configured to perform adaptive-equalization processing of the first signal with a setting value based on the second signal.

9. 发明授权

US09496966B2 Optical communication receiving device and frequency offset compensation method 有权
标题翻译：光通信接收装置和频偏补偿方法
公开(公告)号：US09496966B2
公开(公告)日：2016-11-15
申请号：US14495499
申请日：2014-09-24
申请人： FUJITSU LIMITED
发明人： Kazuhiko Hatae , Nobukazu Koizumi , Koji Nakamuta , Manabu Yamazaki , Tomoki Katou , Masashi Sato , Hisao Nakashima
IPC分类号： H04B10/00 , H04B10/61
CPC分类号： H04B10/6164
摘要： A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; anda residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.
摘要翻译：剩余频率偏移检测单元，被配置为计算载波相位的差的平均值，并输出平均值作为残余频率偏移，其中，所述频偏补偿单元被配置为使用由所述滤波器输出的剩余频率偏移来校正所述频率偏移剩余频偏检测单元。

10. 发明授权

US09660733B2 Signal processing apparatus, signal processing method, and signal processing system 有权
公开(公告)号：US09660733B2
公开(公告)日：2017-05-23
申请号：US14841834
申请日：2015-09-01
申请人： FUJITSU LIMITED
发明人： Masashi Sato , Kazuhiko Hatae , Tomoki Katou , Nobukazu Koizumi , Masato Oota , Yasuo Ohtomo , Manabu Yamazaki , Daisuke Sasaki
IPC分类号： H04B10/61 , H03H21/00 , H03H17/02
CPC分类号： H04B10/616 , H03H17/0294 , H03H21/0012 , H04B10/612
摘要： A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals.

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