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1. 发明授权

US09225356B2 Programming a non-volatile memory (NVM) system having error correction code (ECC) 有权
标题翻译：编程具有纠错码（ECC）的非易失性存储器（NVM）系统
公开(公告)号：US09225356B2
公开(公告)日：2015-12-29
申请号：US13674367
申请日：2012-11-12
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Fuchen Mu , Chen He
IPC分类号： G11C29/00 , H03M13/05 , G11C29/50 , G11C29/52 , G11C13/00 , G06F11/10 , G11C29/04
CPC分类号： H03M13/05 , G06F11/1068 , G11C13/0002 , G11C13/0064 , G11C13/0069 , G11C29/50008 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.
摘要翻译：非易失性半导体存储器件的编程方法包括确定在编程操作期间无法对验证进行编程的位单元数。位单元包括在位单元阵列中的位单元的子集中。该方法还确定是否先前对位单元的子集执行纠错码（ECC）校正。如果在预定数量的编程脉冲之后未能编程验证的比特单元的数量低于阈值数目并且还没有对比特单元的子集执行ECC校正，则程序操作被认为是成功的。

2. 发明授权

US10109356B2 Method and apparatus for stressing a non-volatile memory 有权
公开(公告)号：US10109356B2
公开(公告)日：2018-10-23
申请号：US14631365
申请日：2015-02-25
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Chen He , Richard K. Eguchi , Fuchen Mu , Benjamin A. Schmid , Craig T. Swift , Yanzhuo Wang
IPC分类号： G11C16/14 , G11C29/02 , G11C29/06 , G11C16/04 , G11C29/50
摘要： A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.

3. 发明授权

US09891267B2 Kernel based cluster fault analysis 有权
公开(公告)号：US09891267B2
公开(公告)日：2018-02-13
申请号：US15181649
申请日：2016-06-14
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Nikolas Bradley Sumikawa , Chen He
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185 , G01R31/26 , G01R31/01 , G01R31/18 , H01L21/66
CPC分类号： G01R31/18 , G01R31/01 , G01R31/26 , G01R31/2894 , G01R31/31718 , G01R31/318511 , G01R31/31937 , H01L22/00
摘要： A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.

4. 发明授权

US08947958B2 Latent slow bit detection for non-volatile memory 有权
标题翻译：用于非易失性存储器的潜在慢位检测
公开(公告)号：US08947958B2
公开(公告)日：2015-02-03
申请号：US13647951
申请日：2012-10-09
申请人： Freescale Semiconductor, Inc.
发明人： Fuchen Mu , Chen He , Peter J. Kuhn
IPC分类号： G11C16/04
CPC分类号： G11C29/50004 , G11C16/344
摘要： In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.
摘要翻译：根据至少一个实施例，公开了用于检测潜在慢擦除位的非易失性存储器（NVM）和方法。 NVM单元阵列的至少一部分以减少的擦除偏置被擦除。减小的擦除偏置相对于正常的擦除偏置具有降低的电平。确定最少擦除位（LEB）的至少擦除位（LEB）阈值电压电平。在调整的擦除验证读取阈值电压电平下执行擦除验证。经调整的擦除验证读取阈值电压电平是低于LEB读取阈值电压电平的预定量。确定了一些故障位。故障位是具有高于调整的擦除验证电平的阈值电压的位。响应于故障位数小于故障位阈值，NVM被拒绝。

5. 发明申请

US20140098615A1 LATENT SLOW BIT DETECTION FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的专利慢速位检测
公开(公告)号：US20140098615A1
公开(公告)日：2014-04-10
申请号：US13647951
申请日：2012-10-09
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Fuchen Mu , Chen He , Peter J. Kuhn
IPC分类号： G11C16/06
CPC分类号： G11C29/50004 , G11C16/344
摘要： In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.
摘要翻译：根据至少一个实施例，公开了用于检测潜在慢擦除位的非易失性存储器（NVM）和方法。 NVM单元阵列的至少一部分以减少的擦除偏置被擦除。减小的擦除偏置相对于正常的擦除偏置具有降低的电平。确定最少擦除位（LEB）的至少擦除位（LEB）阈值电压电平。在调整的擦除验证读取阈值电压电平下执行擦除验证。经调整的擦除验证读取阈值电压电平是低于LEB读取阈值电压电平的预定量。确定了一些故障位。故障位是具有高于调整的擦除验证电平的阈值电压的位。响应于故障位数小于故障位阈值，NVM被拒绝。

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